1 /* Copyright (c) 2023 Intel Corporation 2 * SPDX-License-Identifier: Apache-2.0 3 */ 4 5 #ifndef __ZEPHYR_CAVS_LIB_ASM_LDO_MANAGEMENT_H__ 6 #define __ZEPHYR_CAVS_LIB_ASM_LDO_MANAGEMENT_H__ 7 8 #ifdef _ASMLANGUAGE 9 10 #define SHIM_BASE 0x00071F00 11 #define SHIM_LDOCTL 0xA4 12 #define SHIM_LDOCTL_HPSRAM_MASK (3 << 0 | 3 << 16) 13 #define SHIM_LDOCTL_LPSRAM_MASK (3 << 2) 14 #define SHIM_LDOCTL_HPSRAM_LDO_ON (3 << 0 | 3 << 16) 15 #define SHIM_LDOCTL_LPSRAM_LDO_ON (3 << 2) 16 #define SHIM_LDOCTL_HPSRAM_LDO_OFF (0 << 0) 17 #define SHIM_LDOCTL_LPSRAM_LDO_OFF (0 << 2) 18 #define SHIM_LDOCTL_HPSRAM_LDO_BYPASS (BIT(0) | BIT(16)) 19 #define SHIM_LDOCTL_LPSRAM_LDO_BYPASS BIT(2) 20 21 .macro m_cavs_set_ldo_state state, ax 22 movi \ax, (SHIM_BASE + SHIM_LDOCTL) 23 s32i \state, \ax, 0 24 memw 25 /* wait loop > 300ns (min 100ns required) */ 26 movi \ax, 128 27 1 : 28 addi \ax, \ax, -1 29 nop 30 bnez \ax, 1b 31 .endm 32 33 .macro m_cavs_set_hpldo_state state, ax, ay 34 movi \ax, (SHIM_BASE + SHIM_LDOCTL) 35 l32i \ay, \ax, 0 36 37 movi \ax, ~(SHIM_LDOCTL_HPSRAM_MASK) 38 and \ay, \ax, \ay 39 or \state, \ay, \state 40 41 m_cavs_set_ldo_state \state, \ax 42 .endm 43 44 .macro m_cavs_set_lpldo_state state, ax, ay 45 movi \ax, (SHIM_BASE + SHIM_LDOCTL) 46 l32i \ay, \ax, 0 47 /* LP SRAM mask */ 48 movi \ax, ~(SHIM_LDOCTL_LPSRAM_MASK) 49 and \ay, \ax, \ay 50 or \state, \ay, \state 51 52 m_cavs_set_ldo_state \state, \ax 53 .endm 54 55 .macro m_cavs_set_ldo_on_state ax, ay, az 56 movi \ay, (SHIM_BASE + SHIM_LDOCTL) 57 l32i \az, \ay, 0 58 59 movi \ax, ~(SHIM_LDOCTL_HPSRAM_MASK | SHIM_LDOCTL_LPSRAM_MASK) 60 and \az, \ax, \az 61 movi \ax, (SHIM_LDOCTL_HPSRAM_LDO_ON | SHIM_LDOCTL_LPSRAM_LDO_ON) 62 or \ax, \az, \ax 63 64 m_cavs_set_ldo_state \ax, \ay 65 .endm 66 67 .macro m_cavs_set_ldo_off_state ax, ay, az 68 /* wait loop > 300ns (min 100ns required) */ 69 movi \ax, 128 70 1 : 71 addi \ax, \ax, -1 72 nop 73 bnez \ax, 1b 74 movi \ay, (SHIM_BASE + SHIM_LDOCTL) 75 l32i \az, \ay, 0 76 77 movi \ax, ~(SHIM_LDOCTL_HPSRAM_MASK | SHIM_LDOCTL_LPSRAM_MASK) 78 and \az, \az, \ax 79 80 movi \ax, (SHIM_LDOCTL_HPSRAM_LDO_OFF | SHIM_LDOCTL_LPSRAM_LDO_OFF) 81 or \ax, \ax, \az 82 83 s32i \ax, \ay, 0 84 l32i \ax, \ay, 0 85 .endm 86 87 .macro m_cavs_set_ldo_bypass_state ax, ay, az 88 /* wait loop > 300ns (min 100ns required) */ 89 movi \ax, 128 90 1 : 91 addi \ax, \ax, -1 92 nop 93 bnez \ax, 1b 94 movi \ay, (SHIM_BASE + SHIM_LDOCTL) 95 l32i \az, \ay, 0 96 97 movi \ax, ~(SHIM_LDOCTL_HPSRAM_MASK | SHIM_LDOCTL_LPSRAM_MASK) 98 and \az, \az, \ax 99 100 movi \ax, (SHIM_LDOCTL_HPSRAM_LDO_BYPASS | SHIM_LDOCTL_LPSRAM_LDO_BYPASS) 101 or \ax, \ax, \az 102 103 s32i \ax, \ay, 0 104 l32i \ax, \ay, 0 105 .endm 106 107 #endif 108 #endif /* __ZEPHYR_CAVS_LIB_ASM_LDO_MANAGEMENT_H__ */ 109
