1 /*
2 * Copyright (c) 2017 Intel Corporation
3 *
4 * SPDX-License-Identifier: Apache-2.0
5 */
6
7 #ifndef __SOC_H__
8 #define __SOC_H__
9 #include <soc/dport_reg.h>
10 #include <soc/rtc_cntl_reg.h>
11 #include <soc/soc_caps.h>
12 #include <esp32/rom/ets_sys.h>
13 #include <esp32/rom/spi_flash.h>
14 #include <esp_rom_sys.h>
15
16 #include <zephyr/types.h>
17 #include <stdbool.h>
18 #include <zephyr/arch/xtensa/arch.h>
19
20 #include <xtensa/core-macros.h>
21 #include <esp32/clk.h>
22
23 void __esp_platform_start(void);
24
esp32_set_mask32(uint32_t v,uint32_t mem_addr)25 static inline void esp32_set_mask32(uint32_t v, uint32_t mem_addr)
26 {
27 sys_write32(sys_read32(mem_addr) | v, mem_addr);
28 }
29
esp32_clear_mask32(uint32_t v,uint32_t mem_addr)30 static inline void esp32_clear_mask32(uint32_t v, uint32_t mem_addr)
31 {
32 sys_write32(sys_read32(mem_addr) & ~v, mem_addr);
33 }
34
esp_core_id(void)35 static inline uint32_t esp_core_id(void)
36 {
37 uint32_t id;
38
39 __asm__ volatile (
40 "rsr.prid %0\n"
41 "extui %0,%0,13,1" : "=r" (id));
42 return id;
43 }
44
45 extern void esp_rom_intr_matrix_set(int cpu_no, uint32_t model_num, uint32_t intr_num);
46
47 extern int esp_rom_gpio_matrix_in(uint32_t gpio, uint32_t signal_index,
48 bool inverted);
49 extern int esp_rom_gpio_matrix_out(uint32_t gpio, uint32_t signal_index,
50 bool out_inverted,
51 bool out_enabled_inverted);
52
53 extern void esp_rom_uart_attach(void);
54 extern void esp_rom_uart_tx_wait_idle(uint8_t uart_no);
55 extern int esp_rom_uart_tx_one_char(uint8_t chr);
56 extern int esp_rom_uart_rx_one_char(uint8_t *chr);
57
58 extern void esp_rom_Cache_Flush(int cpu);
59 extern void esp_rom_Cache_Read_Enable(int cpu);
60 extern void esp_rom_ets_set_appcpu_boot_addr(void *addr);
61 void esp_appcpu_start(void *entry_point);
62
63 /* ROM functions which read/write internal i2c control bus for PLL, APLL */
64 extern uint8_t esp_rom_i2c_readReg(uint8_t block, uint8_t host_id, uint8_t reg_add);
65 extern void esp_rom_i2c_writeReg(uint8_t block, uint8_t host_id, uint8_t reg_add, uint8_t data);
66
67 /* ROM information related to SPI Flash chip timing and device */
68 extern esp_rom_spiflash_chip_t g_rom_flashchip;
69 extern uint8_t g_rom_spiflash_dummy_len_plus[];
70
71 #endif /* __SOC_H__ */
72
