1# Copyright (c) 2021 Henrik Brix Andersen <henrik@brixandersen.dk>
2# SPDX-License-Identifier: Apache-2.0
3
4config SOC_SERIES_NEORV32
5	bool "NEORV32 Processor"
6	select RISCV
7	select RISCV_ISA_RV32I
8	select RISCV_ISA_EXT_M
9	select RISCV_ISA_EXT_A
10	select RISCV_ISA_EXT_ZICSR
11	select RISCV_ISA_EXT_ZIFENCEI
12	select SOC_FAMILY_RISCV_PRIVILEGED
13	help
14	  Enable support for the NEORV32 Processor (SoC).
15
16	  The NEORV32 CPU implementation must have the following RISC-V ISA
17	  extensions enabled in order to support Zephyr:
18	  - M (Integer Multiplication and Division)
19	  - Zicsr (Control and Status Register (CSR) Instructions)
20
21	  The following NEORV32 CPU ISA extensions are not currently supported
22	  by Zephyr and can safely be disabled:
23	  - A (Atomic Instructions)
24	  - E (Embedded, only 16 integer registers)
25	  - Zbb (Basic Bit Manipulation)
26	  - Zfinx (Floating Point in Integer Registers)
27