1/*
2 * Copyright (c) 2021 Andes Technology Corporation
3 *
4 * SPDX-License-Identifier: Apache-2.0
5 */
6
7#include <zephyr/toolchain.h>
8#include <soc.h>
9
10/* exports */
11GTEXT(entry)
12
13SECTION_FUNC(init, entry)
14	/* Disable linker relaxation before GP register initialization. */
15	.option push
16	.option norelax
17
18#ifdef CONFIG_SOC_ANDES_V5_EXECIT
19	/* Initialize EXECIT table */
20	la t0, _ITB_BASE_
21	csrw NDS_UITB, t0
22#endif
23
24#ifdef CONFIG_ICACHE
25	/* Enable I cache with HW prefetcher. */
26	li t0, (1 << 9) | (1 << 0)
27	csrs NDS_MCACHE_CTL, t0
28#endif
29
30#ifdef CONFIG_DCACHE
31	/*
32	 * Enable D cache with HW prefetcher, D-cache write-around
33	 * (threshold: 4 cache lines), and CM (Coherence Manager).
34	 */
35	li t0, (0x3 << 13)
36	csrc NDS_MCACHE_CTL, t0
37	li t0, (1 << 19) | (1 << 13) | (1 << 10) | (1 << 1)
38	csrs NDS_MCACHE_CTL, t0
39
40	/* Check if CPU support CM or not. */
41	csrr t0, NDS_MCACHE_CTL
42	li t1, (1 << 19)
43	and t0, t0, t1
44	beqz t0, cache_enable_finish
45
46	/* If CPU support CM, check if CM is enabled. */
47	li t1, (1 << 20)
48check_cm_enabled:
49	csrr t0, NDS_MCACHE_CTL
50	and t0, t0, t1
51	beqz t0, check_cm_enabled
52
53cache_enable_finish:
54#endif
55
56	/* Enable misaligned access and non-blocking load */
57	li t0, (1 << 8) | (1 << 6)
58	csrs NDS_MMISC_CTL, t0
59
60	j __start
61
62	.option pop
63