1 /* 2 * Copyright (c) 2021 Andes Technology Corporation 3 * 4 * SPDX-License-Identifier: Apache-2.0 5 */ 6 7 #ifndef __RISCV_ANDES_V5_SOC_V5_H_ 8 #define __RISCV_ANDES_V5_SOC_V5_H_ 9 10 /* Control and Status Registers (CSRs) available for Andes V5 SoCs */ 11 #define NDS_MMISC_CTL 0x7D0 12 #define NDS_MCACHE_CTL 0x7CA 13 #define NDS_MMSC_CFG 0xFC2 14 #define NDS_MXSTATUS 0x7C4 15 #define NDS_UITB 0x800 16 #define NDS_UCODE 0x801 17 18 /* Control and Status Registers (CSRs) available for Andes V5 PMA */ 19 #define NDS_PMACFG0 0xBC0 20 #define NDS_PMACFG1 0xBC1 21 #define NDS_PMACFG2 0xBC2 22 #define NDS_PMACFG3 0xBC3 23 #define NDS_PMAADDR0 0xBD0 24 #define NDS_PMAADDR1 0xBD1 25 #define NDS_PMAADDR2 0xBD2 26 #define NDS_PMAADDR3 0xBD3 27 #define NDS_PMAADDR4 0xBD4 28 #define NDS_PMAADDR5 0xBD5 29 #define NDS_PMAADDR6 0xBD6 30 #define NDS_PMAADDR7 0xBD7 31 #define NDS_PMAADDR8 0xBD8 32 #define NDS_PMAADDR9 0xBD9 33 #define NDS_PMAADDR10 0xBDA 34 #define NDS_PMAADDR11 0xBDB 35 #define NDS_PMAADDR12 0xBDC 36 #define NDS_PMAADDR13 0xBDD 37 #define NDS_PMAADDR14 0xBDE 38 #define NDS_PMAADDR15 0xBDF 39 40 #endif /* __RISCV_ANDES_V5_SOC_V5_H_ */ 41
