1 /*
2 * Copyright (c) 2021 Andes Technology Corporation
3 *
4 * SPDX-License-Identifier: Apache-2.0
5 */
6
7 #define DT_DRV_COMPAT andestech_l2c
8
9 /**
10 * @brief Andes V5 L2 Cache Controller driver
11 */
12
13 #include <zephyr/init.h>
14 #include <zephyr/kernel.h>
15 #include <zephyr/arch/cpu.h>
16 #include <zephyr/drivers/syscon.h>
17 #include <zephyr/logging/log.h>
18 #include <zephyr/arch/riscv/csr.h>
19
20 LOG_MODULE_REGISTER(andes_v5_l2_cache, CONFIG_SOC_LOG_LEVEL);
21
22 /* L2C Register Base Address */
23 #define ANDES_V5_L2C_BASE DT_INST_REG_ADDR(0)
24
25 /* L2C Register Offset */
26 #define L2C_CONFIG (ANDES_V5_L2C_BASE + 0x00)
27 #define L2C_CTRL (ANDES_V5_L2C_BASE + 0x08)
28
29 /* L2C Helper Constant */
30 #define L2C_CONFIG_VER GENMASK64(31, 24)
31 #define L2C_CTRL_CEN BIT(0)
32
33 /* Instruction prefetch depth */
34 #define IPFDPT_FIELD(x) (x << 3)
35 #define L2C_CTRL_IPFDPT_0 IPFDPT_FIELD(0)
36 #define L2C_CTRL_IPFDPT_1 IPFDPT_FIELD(1)
37 #define L2C_CTRL_IPFDPT_2 IPFDPT_FIELD(2)
38 #define L2C_CTRL_IPFDPT_3 IPFDPT_FIELD(3)
39
40 /* Data prefetch depth */
41 #define DPFDPT_FIELD(x) (x << 5)
42 #define L2C_CTRL_DPFDPT_0 DPFDPT_FIELD(0)
43 #define L2C_CTRL_DPFDPT_2 DPFDPT_FIELD(1)
44 #define L2C_CTRL_DPFDPT_4 DPFDPT_FIELD(2)
45 #define L2C_CTRL_DPFDPT_8 DPFDPT_FIELD(3)
46
47 #if DT_HAS_COMPAT_STATUS_OKAY(andestech_atcsmu100)
48 /* SMU Register offset */
49 #define SMU_SYSTEMCFG 0x08
50
51 /* SMU Helper Constant */
52 #define SMU_SYSTEMCFG_L2C BIT(8)
53 #endif
54
andes_v5_l2c_enable(void)55 static void andes_v5_l2c_enable(void)
56 {
57 uint32_t l2c_ctrl = sys_read32(L2C_CTRL);
58
59 /* Enable L2C if I-cache or D-cache is enabled */
60 if (csr_read(NDS_MCACHE_CTL) & BIT_MASK(2)) {
61 uint32_t l2c_config = sys_read32(L2C_CONFIG);
62
63 /* Memory barrier, flush all I/D-Cache before setting L2C */
64 __asm__ volatile ("fence.i");
65
66 l2c_ctrl |= (L2C_CTRL_IPFDPT_3 | L2C_CTRL_DPFDPT_8);
67 sys_write32(l2c_ctrl, L2C_CTRL);
68
69 /* Enable L2C for Gen1 L2C, Gen2 L2C defaults to enable */
70 if ((l2c_config & L2C_CONFIG_VER) < (16 << 24)) {
71 l2c_ctrl = sys_read32(L2C_CTRL);
72 l2c_ctrl |= L2C_CTRL_CEN;
73 sys_write32(l2c_ctrl, L2C_CTRL);
74 }
75 } else {
76 /* Disable L2C */
77 l2c_ctrl &= ~L2C_CTRL_CEN;
78 sys_write32(l2c_ctrl, L2C_CTRL);
79 }
80 }
81
andes_v5_l2c_init(void)82 static int andes_v5_l2c_init(void)
83 {
84 #if DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(syscon), andestech_atcsmu100, okay)
85 const struct device *const syscon_dev = DEVICE_DT_GET(DT_NODELABEL(syscon));
86
87 if (device_is_ready(syscon_dev)) {
88 uint32_t system_cfg;
89
90 syscon_read_reg(syscon_dev, SMU_SYSTEMCFG, &system_cfg);
91
92 /* Platform doesn't have L2C */
93 if (!(system_cfg & SMU_SYSTEMCFG_L2C)) {
94 return -ENODEV;
95 }
96 } else {
97 LOG_ERR("Syscon driver should be initialized before L2 Cache "
98 "initialization.");
99 }
100 #endif
101
102 andes_v5_l2c_enable();
103
104 return 0;
105 }
106
107 SYS_INIT(andes_v5_l2c_init, PRE_KERNEL_2, CONFIG_KERNEL_INIT_PRIORITY_DEFAULT);
108
