1# Copyright (c) 2018 Foundries.io Ltd 2# SPDX-License-Identifier: Apache-2.0 3 4config SOC_OPENISA_RV32M1_RISCV32 5 bool "OpenISA RV32M1 RISC-V cores" 6 select RISCV 7 # The following select is due to limitations in the linker script. 8 # (We can't make it a 'depends on' without causing a dependency loop). 9 select XIP 10 select HAS_RV32M1_LPUART 11 select HAS_RV32M1_LPI2C 12 select HAS_RV32M1_LPSPI 13 select HAS_RV32M1_TPM 14 select ATOMIC_OPERATIONS_C 15 select VEGA_SDK_HAL 16 select RISCV_SOC_INTERRUPT_INIT 17 select CLOCK_CONTROL 18 select HAS_RV32M1_FTFX 19 select HAS_FLASH_LOAD_OFFSET 20 select BUILD_OUTPUT_HEX 21 select RISCV_ISA_RV32I 22 select RISCV_ISA_EXT_M 23 select RISCV_ISA_EXT_A 24 select RISCV_ISA_EXT_ZICSR 25 select RISCV_ISA_EXT_ZIFENCEI 26 help 27 Enable support for OpenISA RV32M1 RISC-V processors. Choose 28 this option to target the RI5CY or ZERO-RISCY core. This 29 option should not be used to target either Arm core. 30
