1# Copyright (c) 2018 Foundries.io Ltd
2# SPDX-License-Identifier: Apache-2.0
3
4# The OpenISA RV32M1 SoC directory in riscv supports the RISC-V
5# cores on OpenISA RV32M1 SoCs.
6#
7# The Zephyr "soc" abstraction isn't a great fit here. These SoCs (in
8# the strict physical sense of "systems on chip") also contain Arm
9# cores, so this type of "soc" doesn't really belong to a single "arch".
10#
11# However, due to constraints imposed by Zephyr's file hierarchy
12# conventions, those "other" cores would need to be supported under a
13# different soc subdirectory, e.g. soc/arm instead of soc/riscv.
14
15choice
16	prompt "OpenISA RV32M1 RISC-V Core Selection"
17	depends on SOC_OPENISA_RV32M1_RISCV32
18
19config SOC_OPENISA_RV32M1_RI5CY
20	bool "OpenISA RV32M1 RI5CY core"
21
22config SOC_OPENISA_RV32M1_ZERO_RISCY
23	bool "OpenISA RV32M1 ZERO-RISCY core"
24
25endchoice
26