1#************************************************************** 2# Create Clock 3#************************************************************** 4 5derive_pll_clocks 6 7# JTAG Signal Constraints constrain the TCK port, assuming a 10MHz JTAG clock and 3ns delays 8create_clock -name {altera_reserved_tck} -period 41.667 [get_ports { altera_reserved_tck }] 9set_input_delay -clock altera_reserved_tck -clock_fall -max 5 [get_ports altera_reserved_tdi] 10set_input_delay -clock altera_reserved_tck -clock_fall -max 5 [get_ports altera_reserved_tms] 11set_output_delay -clock altera_reserved_tck 5 [get_ports altera_reserved_tdo] 12 13create_clock -name {clk_50} -period 20.000 {clk_50} 14 15set_false_path -to [get_ports {user_led[*]}] 16set_false_path -to [get_ports {fpga_reset_n}] 17set_false_path -from [get_ports {fpga_reset_n}] 18 19derive_clock_uncertainty 20 21# QSPI interface 22set_output_delay -clock {clk_50 } -rise -min 11 [get_ports {qspi_io[*]}] 23set_output_delay -clock {clk_50 } -rise -min 11 [get_ports {qspi_clk}] 24set_output_delay -clock {clk_50 } -rise -min 11 [get_ports {qspi_csn}] 25set_input_delay -clock {clk_50 } -rise -min 10 [get_ports {qspi_io[*]}] 26 27# UART 28set_false_path -from * -to [get_ports {uart_tx}] 29
