1 /* 2 * Copyright (c) 2022, NXP 3 * 4 * SPDX-License-Identifier: Apache-2.0 5 */ 6 7 #ifndef ZEPHYR_SOC_ARM64_NXP_IMX9_PINCTRL_SOC_H_ 8 #define ZEPHYR_SOC_ARM64_NXP_IMX9_PINCTRL_SOC_H_ 9 10 #include <zephyr/devicetree.h> 11 #include <zephyr/types.h> 12 #include "fsl_common.h" 13 14 #ifdef __cplusplus 15 extern "C" { 16 #endif 17 18 #define MCUX_IMX_INPUT_SCHMITT_ENABLE_SHIFT IOMUXC1_SW_PAD_CTL_PAD_HYS_SHIFT 19 #define MCUX_IMX_DRIVE_OPEN_DRAIN_SHIFT IOMUXC1_SW_PAD_CTL_PAD_OD_SHIFT 20 #define MCUX_IMX_BIAS_PULL_DOWN_SHIFT IOMUXC1_SW_PAD_CTL_PAD_PD_SHIFT 21 #define MCUX_IMX_BIAS_PULL_UP_SHIFT IOMUXC1_SW_PAD_CTL_PAD_PU_SHIFT 22 #define MCUX_IMX_BIAS_PULL_ENABLE_SHIFT IOMUXC1_SW_PAD_CTL_PAD_PE_SHIFT 23 #define MCUX_IMX_SLEW_RATE_SHIFT IOMUXC1_SW_PAD_CTL_PAD_FSEL1_SHIFT 24 #define MCUX_IMX_DRIVE_STRENGTH_SHIFT IOMUXC1_SW_PAD_CTL_PAD_DSE_SHIFT 25 #define MCUX_IMX_INPUT_ENABLE_SHIFT 23 /* Shift to a bit not used by IOMUXC_SW_PAD_CTL */ 26 #define MCUX_IMX_INPUT_ENABLE(x) ((x >> MCUX_IMX_INPUT_ENABLE_SHIFT) & 0x1) 27 28 #define Z_PINCTRL_MCUX_IMX_PINCFG_INIT(node_id) \ 29 ((DT_PROP(node_id, input_schmitt_enable) << MCUX_IMX_INPUT_SCHMITT_ENABLE_SHIFT) | \ 30 (DT_PROP(node_id, drive_open_drain) << MCUX_IMX_DRIVE_OPEN_DRAIN_SHIFT) | \ 31 (DT_PROP(node_id, bias_pull_down) << MCUX_IMX_BIAS_PULL_DOWN_SHIFT) | \ 32 (DT_PROP(node_id, bias_pull_up) << MCUX_IMX_BIAS_PULL_UP_SHIFT) | \ 33 (DT_ENUM_IDX(node_id, slew_rate) << MCUX_IMX_SLEW_RATE_SHIFT) | \ 34 ((~(0xff << DT_ENUM_IDX(node_id, drive_strength))) << MCUX_IMX_DRIVE_STRENGTH_SHIFT) | \ 35 (DT_PROP(node_id, input_enable) << MCUX_IMX_INPUT_ENABLE_SHIFT)) 36 37 38 /* This struct must be present. It is used by the mcux gpio driver */ 39 struct pinctrl_soc_pinmux { 40 uint32_t mux_register; /*!< IOMUXC SW_PAD_MUX register */ 41 uint32_t config_register; /*!< IOMUXC SW_PAD_CTL register */ 42 uint32_t input_register; /*!< IOMUXC SELECT_INPUT DAISY register */ 43 uint8_t mux_mode: 4; /*!< Mux value for SW_PAD_MUX register */ 44 uint32_t input_daisy:4; /*!< Mux value for SELECT_INPUT_DAISY register */ 45 }; 46 47 struct pinctrl_soc_pin { 48 struct pinctrl_soc_pinmux pinmux; 49 uint32_t pin_ctrl_flags; /*!< value to write to IOMUXC_SW_PAD_CTL register */ 50 }; 51 52 typedef struct pinctrl_soc_pin pinctrl_soc_pin_t; 53 54 /* This definition must be present. It is used by the mcux gpio driver */ 55 #define MCUX_IMX_PINMUX(node_id) \ 56 { \ 57 .mux_register = DT_PROP_BY_IDX(node_id, pinmux, 0), \ 58 .config_register = DT_PROP_BY_IDX(node_id, pinmux, 4), \ 59 .input_register = DT_PROP_BY_IDX(node_id, pinmux, 2), \ 60 .mux_mode = DT_PROP_BY_IDX(node_id, pinmux, 1), \ 61 .input_daisy = DT_PROP_BY_IDX(node_id, pinmux, 3), \ 62 } 63 64 #define Z_PINCTRL_PINMUX(group_id, pin_prop, idx) \ 65 MCUX_IMX_PINMUX(DT_PHANDLE_BY_IDX(group_id, pin_prop, idx)) 66 67 #define Z_PINCTRL_STATE_PIN_INIT(group_id, pin_prop, idx) \ 68 { \ 69 .pinmux = Z_PINCTRL_PINMUX(group_id, pin_prop, idx), \ 70 .pin_ctrl_flags = Z_PINCTRL_MCUX_IMX_PINCFG_INIT(group_id), \ 71 }, 72 73 74 #define Z_PINCTRL_STATE_PINS_INIT(node_id, prop) \ 75 {DT_FOREACH_CHILD_VARGS(DT_PHANDLE(node_id, prop), \ 76 DT_FOREACH_PROP_ELEM, pinmux, Z_PINCTRL_STATE_PIN_INIT)}; \ 77 78 79 #ifdef __cplusplus 80 } 81 #endif 82 83 #endif /* ZEPHYR_SOC_ARM64_NXP_IMX9_PINCTRL_SOC_H_ */ 84
