1 /* 2 * Copyright (c) 2019-2021, Intel Corporation. All rights reserved. 3 * 4 * SPDX-License-Identifier: Apache-2.0 5 */ 6 7 #ifndef SOCFPGA_SYSTEMMANAGER_H 8 #define SOCFPGA_SYSTEMMANAGER_H 9 10 /* System Manager Register Map */ 11 #define SOCFPGA_SYSMGR_REG_BASE 0xffd12000 12 13 #define SOCFPGA_SYSMGR_SDMMC 0x28 14 15 #define SOCFPGA_SYSMGR_FPGAINTF_EN_2 0x6c 16 17 #define SOCFPGA_SYSMGR_EMAC_0 0x44 18 #define SOCFPGA_SYSMGR_EMAC_1 0x48 19 #define SOCFPGA_SYSMGR_EMAC_2 0x4c 20 #define SOCFPGA_SYSMGR_FPGAINTF_EN_3 0x70 21 22 #define SOCFPGA_SYSMGR_NOC_TIMEOUT 0xc0 23 #define SOCFPGA_SYSMGR_NOC_IDLEREQ_SET 0xc4 24 #define SOCFPGA_SYSMGR_NOC_IDLEREQ_CLR 0xc8 25 #define SOCFPGA_SYSMGR_NOC_IDLEREQ_VAL 0xcc 26 #define SOCFPGA_SYSMGR_NOC_IDLEACK 0xd0 27 #define SOCFPGA_SYSMGR_NOC_IDLESTATUS 0xd4 28 29 #define SOCFPGA_SYSMGR_BOOT_SCRATCH_COLD_0 0x200 30 #define SOCFPGA_SYSMGR_BOOT_SCRATCH_COLD_1 0x204 31 #define SOCFPGA_SYSMGR_BOOT_SCRATCH_COLD_2 0x208 32 #define SOCFPGA_SYSMGR_BOOT_SCRATCH_COLD_8 0x220 33 #define SOCFPGA_SYSMGR_BOOT_SCRATCH_COLD_9 0x224 34 35 /* Field Masking */ 36 37 #define SYSMGR_SDMMC_DRVSEL(x) (((x) & 0x7) << 0) 38 #define SYSMGR_SDMMC_SMPLSEL(x) (((x) & 0x7) << 4) 39 40 #define IDLE_DATA_LWSOC2FPGA BIT(0) 41 #define IDLE_DATA_SOC2FPGA BIT(4) 42 #define IDLE_DATA_MASK (IDLE_DATA_LWSOC2FPGA | IDLE_DATA_SOC2FPGA) 43 44 #define SYSMGR_ECC_OCRAM_MASK BIT(1) 45 #define SYSMGR_ECC_DDR0_MASK BIT(16) 46 #define SYSMGR_ECC_DDR1_MASK BIT(17) 47 48 /* Macros */ 49 50 #define SOCFPGA_SYSMGR(_reg) (SOCFPGA_SYSMGR_REG_BASE \ 51 + (SOCFPGA_SYSMGR_##_reg)) 52 53 #endif /* SOCFPGA_SYSTEMMANAGER_H */ 54
