1 /* 2 * Copyright (c) 2019-2021, Intel Corporation. All rights reserved. 3 * 4 * SPDX-License-Identifier: Apache-2.0 5 */ 6 7 #ifndef HANDOFF_H 8 #define HANDOFF_H 9 10 #include <stdint.h> 11 12 #define PLAT_HANDOFF_OFFSET 0xFFE3F000 13 14 #define HANDOFF_MAGIC_HEADER 0x424f4f54 /* BOOT */ 15 #define HANDOFF_MAGIC_PINMUX_SEL 0x504d5558 /* PMUX */ 16 #define HANDOFF_MAGIC_IOCTLR 0x494f4354 /* IOCT */ 17 #define HANDOFF_MAGIC_FPGA 0x46504741 /* FPGA */ 18 #define HANDOFF_MAGIC_IODELAY 0x444c4159 /* DLAY */ 19 #define HANDOFF_MAGIC_CLOCK 0x434c4b53 /* CLKS */ 20 #define HANDOFF_MAGIC_MISC 0x4d495343 /* MISC */ 21 22 struct handoff { 23 /* header */ 24 uint32_t header_magic; 25 uint32_t header_device; 26 uint32_t _pad_0x08_0x10[2]; 27 28 /* pinmux configuration - select */ 29 uint32_t pinmux_sel_magic; 30 uint32_t pinmux_sel_length; 31 uint32_t _pad_0x18_0x20[2]; 32 uint32_t pinmux_sel_array[96]; /* offset, value */ 33 34 /* pinmux configuration - io control */ 35 uint32_t pinmux_io_magic; 36 uint32_t pinmux_io_length; 37 uint32_t _pad_0x1a8_0x1b0[2]; 38 uint32_t pinmux_io_array[96]; /* offset, value */ 39 40 /* pinmux configuration - use fpga switch */ 41 uint32_t pinmux_fpga_magic; 42 uint32_t pinmux_fpga_length; 43 uint32_t _pad_0x338_0x340[2]; 44 uint32_t pinmux_fpga_array[42]; /* offset, value */ 45 uint32_t _pad_0x3e8_0x3f0[2]; 46 47 /* pinmux configuration - io delay */ 48 uint32_t pinmux_delay_magic; 49 uint32_t pinmux_delay_length; 50 uint32_t _pad_0x3f8_0x400[2]; 51 uint32_t pinmux_iodelay_array[96]; /* offset, value */ 52 53 /* clock configuration */ 54 uint32_t clock_magic; 55 uint32_t clock_length; 56 uint32_t _pad_0x588_0x590[2]; 57 uint32_t main_pll_mpuclk; 58 uint32_t main_pll_nocclk; 59 uint32_t main_pll_nocdiv; 60 uint32_t main_pll_pllglob; 61 uint32_t main_pll_fdbck; 62 uint32_t main_pll_pllc0; 63 uint32_t main_pll_pllc1; 64 uint32_t main_pll_pllc2; 65 uint32_t main_pll_pllc3; 66 uint32_t main_pll_pllm; 67 uint32_t per_pll_emacctl; 68 uint32_t per_pll_gpiodiv; 69 uint32_t per_pll_pllglob; 70 uint32_t per_pll_fdbck; 71 uint32_t per_pll_pllc0; 72 uint32_t per_pll_pllc1; 73 uint32_t per_pll_pllc2; 74 uint32_t per_pll_pllc3; 75 uint32_t per_pll_pllm; 76 uint32_t alt_emacactr; 77 uint32_t alt_emacbctr; 78 uint32_t alt_emacptpctr; 79 uint32_t alt_gpiodbctr; 80 uint32_t alt_sdmmcctr; 81 uint32_t alt_s2fuser0ctr; 82 uint32_t alt_s2fuser1ctr; 83 uint32_t alt_psirefctr; 84 uint32_t hps_osc_clk_h; 85 uint32_t fpga_clk_hz; 86 uint32_t _pad_0x604_0x610[3]; 87 88 /* misc configuration */ 89 uint32_t misc_magic; 90 uint32_t misc_length; 91 uint32_t _pad_0x618_0x620[2]; 92 }; 93 94 #endif 95
