1 /*
2  * Copyright (c) 2023 STMicroelectronics
3  *
4  * SPDX-License-Identifier: Apache-2.0
5  */
6 
7 /**
8  * @file
9  * @brief System/hardware module for STM32WBA processor
10  */
11 
12 #include <zephyr/device.h>
13 #include <zephyr/init.h>
14 #include <stm32_ll_bus.h>
15 #include <stm32_ll_pwr.h>
16 #include <stm32_ll_icache.h>
17 #include <zephyr/arch/cpu.h>
18 #include <zephyr/irq.h>
19 #include <zephyr/logging/log.h>
20 
21 #include <cmsis_core.h>
22 
23 #define LOG_LEVEL CONFIG_SOC_LOG_LEVEL
24 LOG_MODULE_REGISTER(soc);
25 
26 /**
27  * @brief Perform basic hardware initialization at boot.
28  *
29  * This needs to be run from the very beginning.
30  * So the init priority has to be 0 (zero).
31  *
32  * @return 0
33  */
stm32wba_init(void)34 static int stm32wba_init(void)
35 {
36 	/* Enable instruction cache in 1-way (direct mapped cache) */
37 	LL_ICACHE_SetMode(LL_ICACHE_1WAY);
38 	LL_ICACHE_Enable();
39 
40 	/* Update CMSIS SystemCoreClock variable (HCLK) */
41 	/* At reset, system core clock is set to 16 MHz from HSI */
42 	SystemCoreClock = 16000000;
43 
44 	/* Enable PWR */
45 	LL_AHB4_GRP1_EnableClock(LL_AHB4_GRP1_PERIPH_PWR);
46 
47 	return 0;
48 }
49 
50 SYS_INIT(stm32wba_init, PRE_KERNEL_1, 0);
51