1 /*
2  * Copyright (c) 2020 Linaro Limited
3  *
4  * SPDX-License-Identifier: Apache-2.0
5  */
6 
7 /**
8  * @file
9  * @brief System/hardware module for STM32L5 processor
10  */
11 
12 #include <zephyr/device.h>
13 #include <zephyr/init.h>
14 #include <stm32_ll_bus.h>
15 #include <stm32_ll_pwr.h>
16 #include <stm32l5xx_ll_icache.h>
17 #include <zephyr/logging/log.h>
18 
19 #include <cmsis_core.h>
20 
21 #define LOG_LEVEL CONFIG_SOC_LOG_LEVEL
22 LOG_MODULE_REGISTER(soc);
23 
24 /**
25  * @brief Perform basic hardware initialization at boot.
26  *
27  * This needs to be run from the very beginning.
28  * So the init priority has to be 0 (zero).
29  *
30  * @return 0
31  */
stm32l5_init(void)32 static int stm32l5_init(void)
33 {
34 	/* Enable ICACHE */
35 	while (LL_ICACHE_IsActiveFlag_BUSY()) {
36 	}
37 	LL_ICACHE_Enable();
38 
39 	/* Update CMSIS SystemCoreClock variable (HCLK) */
40 	/* At reset, system core clock is set to 4 MHz from MSI */
41 	SystemCoreClock = 4000000;
42 
43 	/* Enable Scale 0 to achieve 110MHz */
44 	LL_APB1_GRP1_EnableClock(LL_APB1_GRP1_PERIPH_PWR);
45 	LL_PWR_SetRegulVoltageScaling(LL_PWR_REGU_VOLTAGE_SCALE0);
46 
47 	/* Disable USB Type-C dead battery pull-down behavior */
48 	LL_PWR_DisableUCPDDeadBattery();
49 
50 	return 0;
51 }
52 
53 SYS_INIT(stm32l5_init, PRE_KERNEL_1, 0);
54