1 /* 2 * Copyright (c) 2018 Endre Karlson <endre.karlson@gmail.com> 3 * 4 * SPDX-License-Identifier: Apache-2.0 5 */ 6 7 /** 8 * @file 9 * @brief System/hardware module for STM32L0 processor 10 */ 11 12 #include <zephyr/device.h> 13 #include <zephyr/init.h> 14 #include <zephyr/linker/linker-defs.h> 15 #include <string.h> 16 #include <stm32_ll_bus.h> 17 #include <stm32_ll_pwr.h> 18 #include <stm32_ll_bus.h> 19 20 #include <cmsis_core.h> 21 22 /** 23 * @brief Perform basic hardware initialization at boot. 24 * 25 * This needs to be run from the very beginning. 26 * So the init priority has to be 0 (zero). 27 * 28 * @return 0 29 */ stm32l0_init(void)30static int stm32l0_init(void) 31 { 32 /* Update CMSIS SystemCoreClock variable (HCLK) */ 33 /* At reset, system core clock is set to 2.1 MHz from MSI */ 34 SystemCoreClock = 2097152; 35 36 /* Default Voltage scaling range selection (range2) 37 * doesn't allow to configure Max frequency 38 * switch to range1 to match any frequency 39 */ 40 LL_APB1_GRP1_EnableClock(LL_APB1_GRP1_PERIPH_PWR); 41 LL_PWR_SetRegulVoltageScaling(LL_PWR_REGU_VOLTAGE_SCALE1); 42 43 /* On STM32L0, there are some hardfault when enabling DBGMCU bit: 44 * Sleep, Stop or Standby. 45 * See https://github.com/zephyrproject-rtos/zephyr/issues/#37119 46 * For unclear reason, enabling DMA clock fixes this issue 47 * (similarly than it fixes 48 * https://github.com/zephyrproject-rtos/zephyr/issues/#34324 ) 49 */ 50 LL_AHB1_GRP1_EnableClock(LL_AHB1_GRP1_PERIPH_DMA1); 51 52 return 0; 53 } 54 55 SYS_INIT(stm32l0_init, PRE_KERNEL_1, 0); 56
