1 /* 2 * Copyright (c) 2019 Linaro Limited 3 * 4 * SPDX-License-Identifier: Apache-2.0 5 */ 6 7 /** 8 * @file 9 * @brief System/hardware module for STM32H7 CM4 processor 10 */ 11 12 #include <zephyr/kernel.h> 13 #include <zephyr/device.h> 14 #include <zephyr/init.h> 15 #include <soc.h> 16 #include <stm32_ll_bus.h> 17 #include <stm32_ll_cortex.h> 18 #include <stm32_ll_pwr.h> 19 #include <stm32_ll_rcc.h> 20 #include <stm32_ll_system.h> 21 #include "stm32_hsem.h" 22 23 #include <cmsis_core.h> 24 25 /** 26 * @brief Perform basic hardware initialization at boot. 27 * 28 * This needs to be run from the very beginning. 29 * So the init priority has to be 0 (zero). 30 * 31 * @return 0 32 */ stm32h7_m4_init(void)33static int stm32h7_m4_init(void) 34 { 35 /* Enable ART Flash cache accelerator */ 36 LL_AHB1_GRP1_EnableClock(LL_AHB1_GRP1_PERIPH_ART); 37 LL_ART_SetBaseAddress(DT_REG_ADDR(DT_CHOSEN(zephyr_flash))); 38 LL_ART_Enable(); 39 40 /* In case CM4 has not been forced boot by CM7, 41 * CM4 needs to wait until CM7 has setup clock configuration 42 */ 43 if (!LL_RCC_IsCM4BootForced()) { 44 /* 45 * Domain D2 is waiting for Cortex-M7 to perform 46 * system initialization 47 * (system clock config, external memory configuration.. ). 48 * End of system initialization is reached when CM7 takes HSEM. 49 */ 50 LL_AHB4_GRP1_EnableClock(LL_AHB4_GRP1_PERIPH_HSEM); 51 while ((HSEM->RLR[CFG_HW_ENTRY_STOP_MODE_SEMID] & HSEM_R_LOCK) 52 != HSEM_R_LOCK) 53 ; 54 } 55 56 return 0; 57 } 58 59 SYS_INIT(stm32h7_m4_init, PRE_KERNEL_1, 0); 60
