1 /*
2 * Copyright (c) 2021 IoT.bzh
3 *
4 * SPDX-License-Identifier: Apache-2.0
5 *
6 */
7
8 #include "pinctrl_soc.h"
9 #include <zephyr/dt-bindings/pinctrl/renesas/pinctrl-r8a77951.h>
10
11 const struct pfc_drive_reg pfc_drive_regs[] = {
12 /* DRVCTRL0 */
13 { 0x0300, {
14 { PIN_QSPI0_SPCLK, 28, 2 }, /* QSPI0_SPCLK */
15 { PIN_QSPI0_MOSI_IO0, 24, 2 }, /* QSPI0_MOSI_IO0 */
16 { PIN_QSPI0_MISO_IO1, 20, 2 }, /* QSPI0_MISO_IO1 */
17 { PIN_QSPI0_IO2, 16, 2 }, /* QSPI0_IO2 */
18 { PIN_QSPI0_IO3, 12, 2 }, /* QSPI0_IO3 */
19 { PIN_QSPI0_SSL, 8, 2 }, /* QSPI0_SSL */
20 { PIN_QSPI1_SPCLK, 4, 2 }, /* QSPI1_SPCLK */
21 { PIN_QSPI1_MOSI_IO0, 0, 2 }, /* QSPI1_MOSI_IO0 */
22 } },
23 /* DRVCTRL1 */
24 { 0x0304, {
25 { PIN_QSPI1_MISO_IO1, 28, 2 }, /* QSPI1_MISO_IO1 */
26 { PIN_QSPI1_IO2, 24, 2 }, /* QSPI1_IO2 */
27 { PIN_QSPI1_IO3, 20, 2 }, /* QSPI1_IO3 */
28 { PIN_QSPI1_SSL, 16, 2 }, /* QSPI1_SSL */
29 { PIN_RPC_INT_N, 12, 2 }, /* RPC_INT# */
30 { PIN_RPC_WP_N, 8, 2 }, /* RPC_WP# */
31 { PIN_RPC_RESET_N, 4, 2 }, /* RPC_RESET# */
32 { PIN_AVB_RX_CTL, 0, 3 }, /* AVB_RX_CTL */
33 } },
34 /* DRVCTRL2 */
35 { 0x0308, {
36 { PIN_AVB_RXC, 28, 3 }, /* AVB_RXC */
37 { PIN_AVB_RD0, 24, 3 }, /* AVB_RD0 */
38 { PIN_AVB_RD1, 20, 3 }, /* AVB_RD1 */
39 { PIN_AVB_RD2, 16, 3 }, /* AVB_RD2 */
40 { PIN_AVB_RD3, 12, 3 }, /* AVB_RD3 */
41 { PIN_AVB_TX_CTL, 8, 3 }, /* AVB_TX_CTL */
42 { PIN_AVB_TXC, 4, 3 }, /* AVB_TXC */
43 { PIN_AVB_TD0, 0, 3 }, /* AVB_TD0 */
44 } },
45 /* DRVCTRL3 */
46 { 0x030c, {
47 { PIN_AVB_TD1, 28, 3 }, /* AVB_TD1 */
48 { PIN_AVB_TD2, 24, 3 }, /* AVB_TD2 */
49 { PIN_AVB_TD3, 20, 3 }, /* AVB_TD3 */
50 { PIN_AVB_TXCREFCLK, 16, 3 }, /* AVB_TXCREFCLK */
51 { PIN_AVB_MDIO, 12, 3 }, /* AVB_MDIO */
52 { RCAR_GP_PIN(2, 9), 8, 3 }, /* AVB_MDC */
53 { RCAR_GP_PIN(2, 10), 4, 3 }, /* AVB_MAGIC */
54 { RCAR_GP_PIN(2, 11), 0, 3 }, /* AVB_PHY_INT */
55 } },
56 /* DRVCTRL4 */
57 { 0x0310, {
58 { RCAR_GP_PIN(2, 12), 28, 3 }, /* AVB_LINK */
59 { RCAR_GP_PIN(2, 13), 24, 3 }, /* AVB_AVTP_MATCH */
60 { RCAR_GP_PIN(2, 14), 20, 3 }, /* AVB_AVTP_CAPTURE */
61 { RCAR_GP_PIN(2, 0), 16, 3 }, /* IRQ0 */
62 { RCAR_GP_PIN(2, 1), 12, 3 }, /* IRQ1 */
63 { RCAR_GP_PIN(2, 2), 8, 3 }, /* IRQ2 */
64 { RCAR_GP_PIN(2, 3), 4, 3 }, /* IRQ3 */
65 { RCAR_GP_PIN(2, 4), 0, 3 }, /* IRQ4 */
66 } },
67 /* DRVCTRL5 */
68 { 0x0314, {
69 { RCAR_GP_PIN(2, 5), 28, 3 }, /* IRQ5 */
70 { RCAR_GP_PIN(2, 6), 24, 3 }, /* PWM0 */
71 { RCAR_GP_PIN(2, 7), 20, 3 }, /* PWM1 */
72 { RCAR_GP_PIN(2, 8), 16, 3 }, /* PWM2 */
73 { RCAR_GP_PIN(1, 0), 12, 3 }, /* A0 */
74 { RCAR_GP_PIN(1, 1), 8, 3 }, /* A1 */
75 { RCAR_GP_PIN(1, 2), 4, 3 }, /* A2 */
76 { RCAR_GP_PIN(1, 3), 0, 3 }, /* A3 */
77 } },
78 /* DRVCTRL6 */
79 { 0x0318, {
80 { RCAR_GP_PIN(1, 4), 28, 3 }, /* A4 */
81 { RCAR_GP_PIN(1, 5), 24, 3 }, /* A5 */
82 { RCAR_GP_PIN(1, 6), 20, 3 }, /* A6 */
83 { RCAR_GP_PIN(1, 7), 16, 3 }, /* A7 */
84 { RCAR_GP_PIN(1, 8), 12, 3 }, /* A8 */
85 { RCAR_GP_PIN(1, 9), 8, 3 }, /* A9 */
86 { RCAR_GP_PIN(1, 10), 4, 3 }, /* A10 */
87 { RCAR_GP_PIN(1, 11), 0, 3 }, /* A11 */
88 } },
89 /* DRVCTRL7 */
90 { 0x031c, {
91 { RCAR_GP_PIN(1, 12), 28, 3 }, /* A12 */
92 { RCAR_GP_PIN(1, 13), 24, 3 }, /* A13 */
93 { RCAR_GP_PIN(1, 14), 20, 3 }, /* A14 */
94 { RCAR_GP_PIN(1, 15), 16, 3 }, /* A15 */
95 { RCAR_GP_PIN(1, 16), 12, 3 }, /* A16 */
96 { RCAR_GP_PIN(1, 17), 8, 3 }, /* A17 */
97 { RCAR_GP_PIN(1, 18), 4, 3 }, /* A18 */
98 { RCAR_GP_PIN(1, 19), 0, 3 }, /* A19 */
99 } },
100 /* DRVCTRL8 */
101 { 0x0320, {
102 { RCAR_GP_PIN(1, 28), 28, 3 }, /* CLKOUT */
103 { RCAR_GP_PIN(1, 20), 24, 3 }, /* CS0 */
104 { RCAR_GP_PIN(1, 21), 20, 3 }, /* CS1_A26 */
105 { RCAR_GP_PIN(1, 22), 16, 3 }, /* BS */
106 { RCAR_GP_PIN(1, 23), 12, 3 }, /* RD */
107 { RCAR_GP_PIN(1, 24), 8, 3 }, /* RD_WR */
108 { RCAR_GP_PIN(1, 25), 4, 3 }, /* WE0 */
109 { RCAR_GP_PIN(1, 26), 0, 3 }, /* WE1 */
110 } },
111 /* DRVCTRL9 */
112 { 0x0324, {
113 { RCAR_GP_PIN(1, 27), 28, 3 }, /* EX_WAIT0 */
114 { PIN_PRESETOUT_N, 24, 3 }, /* PRESETOUT# */
115 { RCAR_GP_PIN(0, 0), 20, 3 }, /* D0 */
116 { RCAR_GP_PIN(0, 1), 16, 3 }, /* D1 */
117 { RCAR_GP_PIN(0, 2), 12, 3 }, /* D2 */
118 { RCAR_GP_PIN(0, 3), 8, 3 }, /* D3 */
119 { RCAR_GP_PIN(0, 4), 4, 3 }, /* D4 */
120 { RCAR_GP_PIN(0, 5), 0, 3 }, /* D5 */
121 } },
122 /* DRVCTRL10 */
123 { 0x0328, {
124 { RCAR_GP_PIN(0, 6), 28, 3 }, /* D6 */
125 { RCAR_GP_PIN(0, 7), 24, 3 }, /* D7 */
126 { RCAR_GP_PIN(0, 8), 20, 3 }, /* D8 */
127 { RCAR_GP_PIN(0, 9), 16, 3 }, /* D9 */
128 { RCAR_GP_PIN(0, 10), 12, 3 }, /* D10 */
129 { RCAR_GP_PIN(0, 11), 8, 3 }, /* D11 */
130 { RCAR_GP_PIN(0, 12), 4, 3 }, /* D12 */
131 { RCAR_GP_PIN(0, 13), 0, 3 }, /* D13 */
132 } },
133 /* DRVCTRL11 */
134 { 0x032c, {
135 { RCAR_GP_PIN(0, 14), 28, 3 }, /* D14 */
136 { RCAR_GP_PIN(0, 15), 24, 3 }, /* D15 */
137 { RCAR_GP_PIN(7, 0), 20, 3 }, /* AVS1 */
138 { RCAR_GP_PIN(7, 1), 16, 3 }, /* AVS2 */
139 { RCAR_GP_PIN(7, 2), 12, 3 }, /* GP7_02 */
140 { RCAR_GP_PIN(7, 3), 8, 3 }, /* GP7_03 */
141 { PIN_DU_DOTCLKIN0, 4, 2 }, /* DU_DOTCLKIN0 */
142 { PIN_DU_DOTCLKIN1, 0, 2 }, /* DU_DOTCLKIN1 */
143 } },
144 /* DRVCTRL12 */
145 { 0x0330, {
146 { PIN_DU_DOTCLKIN2, 28, 2 }, /* DU_DOTCLKIN2 */
147 { PIN_DU_DOTCLKIN3, 24, 2 }, /* DU_DOTCLKIN3 */
148 { PIN_FSCLKST_N, 20, 2 }, /* FSCLKST# */
149 { PIN_TMS, 4, 2 }, /* TMS */
150 } },
151 /* DRVCTRL13 */
152 { 0x0334, {
153 { PIN_TDO, 28, 2 }, /* TDO */
154 { PIN_ASEBRK, 24, 2 }, /* ASEBRK */
155 { RCAR_GP_PIN(3, 0), 20, 3 }, /* SD0_CLK */
156 { RCAR_GP_PIN(3, 1), 16, 3 }, /* SD0_CMD */
157 { RCAR_GP_PIN(3, 2), 12, 3 }, /* SD0_DAT0 */
158 { RCAR_GP_PIN(3, 3), 8, 3 }, /* SD0_DAT1 */
159 { RCAR_GP_PIN(3, 4), 4, 3 }, /* SD0_DAT2 */
160 { RCAR_GP_PIN(3, 5), 0, 3 }, /* SD0_DAT3 */
161 } },
162 /* DRVCTRL14 */
163 { 0x0338, {
164 { RCAR_GP_PIN(3, 6), 28, 3 }, /* SD1_CLK */
165 { RCAR_GP_PIN(3, 7), 24, 3 }, /* SD1_CMD */
166 { RCAR_GP_PIN(3, 8), 20, 3 }, /* SD1_DAT0 */
167 { RCAR_GP_PIN(3, 9), 16, 3 }, /* SD1_DAT1 */
168 { RCAR_GP_PIN(3, 10), 12, 3 }, /* SD1_DAT2 */
169 { RCAR_GP_PIN(3, 11), 8, 3 }, /* SD1_DAT3 */
170 { RCAR_GP_PIN(4, 0), 4, 3 }, /* SD2_CLK */
171 { RCAR_GP_PIN(4, 1), 0, 3 }, /* SD2_CMD */
172 } },
173 /* DRVCTRL15 */
174 { 0x033c, {
175 { RCAR_GP_PIN(4, 2), 28, 3 }, /* SD2_DAT0 */
176 { RCAR_GP_PIN(4, 3), 24, 3 }, /* SD2_DAT1 */
177 { RCAR_GP_PIN(4, 4), 20, 3 }, /* SD2_DAT2 */
178 { RCAR_GP_PIN(4, 5), 16, 3 }, /* SD2_DAT3 */
179 { RCAR_GP_PIN(4, 6), 12, 3 }, /* SD2_DS */
180 { RCAR_GP_PIN(4, 7), 8, 3 }, /* SD3_CLK */
181 { RCAR_GP_PIN(4, 8), 4, 3 }, /* SD3_CMD */
182 { RCAR_GP_PIN(4, 9), 0, 3 }, /* SD3_DAT0 */
183 } },
184 /* DRVCTRL16 */
185 { 0x0340, {
186 { RCAR_GP_PIN(4, 10), 28, 3 }, /* SD3_DAT1 */
187 { RCAR_GP_PIN(4, 11), 24, 3 }, /* SD3_DAT2 */
188 { RCAR_GP_PIN(4, 12), 20, 3 }, /* SD3_DAT3 */
189 { RCAR_GP_PIN(4, 13), 16, 3 }, /* SD3_DAT4 */
190 { RCAR_GP_PIN(4, 14), 12, 3 }, /* SD3_DAT5 */
191 { RCAR_GP_PIN(4, 15), 8, 3 }, /* SD3_DAT6 */
192 { RCAR_GP_PIN(4, 16), 4, 3 }, /* SD3_DAT7 */
193 { RCAR_GP_PIN(4, 17), 0, 3 }, /* SD3_DS */
194 } },
195 /* DRVCTRL17 */
196 { 0x0344, {
197 { RCAR_GP_PIN(3, 12), 28, 3 }, /* SD0_CD */
198 { RCAR_GP_PIN(3, 13), 24, 3 }, /* SD0_WP */
199 { RCAR_GP_PIN(3, 14), 20, 3 }, /* SD1_CD */
200 { RCAR_GP_PIN(3, 15), 16, 3 }, /* SD1_WP */
201 { RCAR_GP_PIN(5, 0), 12, 3 }, /* SCK0 */
202 { RCAR_GP_PIN(5, 1), 8, 3 }, /* RX0 */
203 { RCAR_GP_PIN(5, 2), 4, 3 }, /* TX0 */
204 { RCAR_GP_PIN(5, 3), 0, 3 }, /* CTS0 */
205 } },
206 /* DRVCTRL18 */
207 { 0x0348, {
208 { RCAR_GP_PIN(5, 4), 28, 3 }, /* RTS0 */
209 { RCAR_GP_PIN(5, 5), 24, 3 }, /* RX1 */
210 { RCAR_GP_PIN(5, 6), 20, 3 }, /* TX1 */
211 { RCAR_GP_PIN(5, 7), 16, 3 }, /* CTS1 */
212 { RCAR_GP_PIN(5, 8), 12, 3 }, /* RTS1 */
213 { RCAR_GP_PIN(5, 9), 8, 3 }, /* SCK2 */
214 { RCAR_GP_PIN(5, 10), 4, 3 }, /* TX2 */
215 { RCAR_GP_PIN(5, 11), 0, 3 }, /* RX2 */
216 } },
217 /* DRVCTRL19 */
218 { 0x034c, {
219 { RCAR_GP_PIN(5, 12), 28, 3 }, /* HSCK0 */
220 { RCAR_GP_PIN(5, 13), 24, 3 }, /* HRX0 */
221 { RCAR_GP_PIN(5, 14), 20, 3 }, /* HTX0 */
222 { RCAR_GP_PIN(5, 15), 16, 3 }, /* HCTS0 */
223 { RCAR_GP_PIN(5, 16), 12, 3 }, /* HRTS0 */
224 { RCAR_GP_PIN(5, 17), 8, 3 }, /* MSIOF0_SCK */
225 { RCAR_GP_PIN(5, 18), 4, 3 }, /* MSIOF0_SYNC */
226 { RCAR_GP_PIN(5, 19), 0, 3 }, /* MSIOF0_SS1 */
227 } },
228 /* DRVCTRL20 */
229 { 0x0350, {
230 { RCAR_GP_PIN(5, 20), 28, 3 }, /* MSIOF0_TXD */
231 { RCAR_GP_PIN(5, 21), 24, 3 }, /* MSIOF0_SS2 */
232 { RCAR_GP_PIN(5, 22), 20, 3 }, /* MSIOF0_RXD */
233 { RCAR_GP_PIN(5, 23), 16, 3 }, /* MLB_CLK */
234 { RCAR_GP_PIN(5, 24), 12, 3 }, /* MLB_SIG */
235 { RCAR_GP_PIN(5, 25), 8, 3 }, /* MLB_DAT */
236 { PIN_MLB_REF, 4, 3 }, /* MLB_REF */
237 { RCAR_GP_PIN(6, 0), 0, 3 }, /* SSI_SCK01239 */
238 } },
239 /* DRVCTRL21 */
240 { 0x0354, {
241 { RCAR_GP_PIN(6, 1), 28, 3 }, /* SSI_WS01239 */
242 { RCAR_GP_PIN(6, 2), 24, 3 }, /* SSI_SDATA0 */
243 { RCAR_GP_PIN(6, 3), 20, 3 }, /* SSI_SDATA1 */
244 { RCAR_GP_PIN(6, 4), 16, 3 }, /* SSI_SDATA2 */
245 { RCAR_GP_PIN(6, 5), 12, 3 }, /* SSI_SCK349 */
246 { RCAR_GP_PIN(6, 6), 8, 3 }, /* SSI_WS349 */
247 { RCAR_GP_PIN(6, 7), 4, 3 }, /* SSI_SDATA3 */
248 { RCAR_GP_PIN(6, 8), 0, 3 }, /* SSI_SCK4 */
249 } },
250 /* DRVCTRL22 */
251 { 0x0358, {
252 { RCAR_GP_PIN(6, 9), 28, 3 }, /* SSI_WS4 */
253 { RCAR_GP_PIN(6, 10), 24, 3 }, /* SSI_SDATA4 */
254 { RCAR_GP_PIN(6, 11), 20, 3 }, /* SSI_SCK5 */
255 { RCAR_GP_PIN(6, 12), 16, 3 }, /* SSI_WS5 */
256 { RCAR_GP_PIN(6, 13), 12, 3 }, /* SSI_SDATA5 */
257 { RCAR_GP_PIN(6, 14), 8, 3 }, /* SSI_SCK6 */
258 { RCAR_GP_PIN(6, 15), 4, 3 }, /* SSI_WS6 */
259 { RCAR_GP_PIN(6, 16), 0, 3 }, /* SSI_SDATA6 */
260 } },
261 /* DRVCTRL23 */
262 { 0x035c, {
263 { RCAR_GP_PIN(6, 17), 28, 3 }, /* SSI_SCK78 */
264 { RCAR_GP_PIN(6, 18), 24, 3 }, /* SSI_WS78 */
265 { RCAR_GP_PIN(6, 19), 20, 3 }, /* SSI_SDATA7 */
266 { RCAR_GP_PIN(6, 20), 16, 3 }, /* SSI_SDATA8 */
267 { RCAR_GP_PIN(6, 21), 12, 3 }, /* SSI_SDATA9 */
268 { RCAR_GP_PIN(6, 22), 8, 3 }, /* AUDIO_CLKA */
269 { RCAR_GP_PIN(6, 23), 4, 3 }, /* AUDIO_CLKB */
270 { RCAR_GP_PIN(6, 24), 0, 3 }, /* USB0_PWEN */
271 } },
272 /* DRVCTRL24 */
273 { 0x0360, {
274 { RCAR_GP_PIN(6, 25), 28, 3 }, /* USB0_OVC */
275 { RCAR_GP_PIN(6, 26), 24, 3 }, /* USB1_PWEN */
276 { RCAR_GP_PIN(6, 27), 20, 3 }, /* USB1_OVC */
277 { RCAR_GP_PIN(6, 28), 16, 3 }, /* USB30_PWEN */
278 { RCAR_GP_PIN(6, 29), 12, 3 }, /* USB30_OVC */
279 { RCAR_GP_PIN(6, 30), 8, 3 }, /* GP6_30/USB2_CH3_PWEN */
280 { RCAR_GP_PIN(6, 31), 4, 3 }, /* GP6_31/USB2_CH3_OVC */
281 } },
282 { },
283 };
284
285 #define PFC_BIAS_REG(r1, r2) \
286 .puen = r1, \
287 .pud = r2, \
288 .pins =
289
290 const struct pfc_bias_reg pfc_bias_regs[] = {
291 { PFC_BIAS_REG(0x0400, 0x0440) { /* PUEN0, PUD0 */
292 [0] = PIN_QSPI0_SPCLK, /* QSPI0_SPCLK */
293 [1] = PIN_QSPI0_MOSI_IO0, /* QSPI0_MOSI_IO0 */
294 [2] = PIN_QSPI0_MISO_IO1, /* QSPI0_MISO_IO1 */
295 [3] = PIN_QSPI0_IO2, /* QSPI0_IO2 */
296 [4] = PIN_QSPI0_IO3, /* QSPI0_IO3 */
297 [5] = PIN_QSPI0_SSL, /* QSPI0_SSL */
298 [6] = PIN_QSPI1_SPCLK, /* QSPI1_SPCLK */
299 [7] = PIN_QSPI1_MOSI_IO0, /* QSPI1_MOSI_IO0 */
300 [8] = PIN_QSPI1_MISO_IO1, /* QSPI1_MISO_IO1 */
301 [9] = PIN_QSPI1_IO2, /* QSPI1_IO2 */
302 [10] = PIN_QSPI1_IO3, /* QSPI1_IO3 */
303 [11] = PIN_QSPI1_SSL, /* QSPI1_SSL */
304 [12] = PIN_RPC_INT_N, /* RPC_INT# */
305 [13] = PIN_RPC_WP_N, /* RPC_WP# */
306 [14] = PIN_RPC_RESET_N, /* RPC_RESET# */
307 [15] = PIN_AVB_RX_CTL, /* AVB_RX_CTL */
308 [16] = PIN_AVB_RXC, /* AVB_RXC */
309 [17] = PIN_AVB_RD0, /* AVB_RD0 */
310 [18] = PIN_AVB_RD1, /* AVB_RD1 */
311 [19] = PIN_AVB_RD2, /* AVB_RD2 */
312 [20] = PIN_AVB_RD3, /* AVB_RD3 */
313 [21] = PIN_AVB_TX_CTL, /* AVB_TX_CTL */
314 [22] = PIN_AVB_TXC, /* AVB_TXC */
315 [23] = PIN_AVB_TD0, /* AVB_TD0 */
316 [24] = PIN_AVB_TD1, /* AVB_TD1 */
317 [25] = PIN_AVB_TD2, /* AVB_TD2 */
318 [26] = PIN_AVB_TD3, /* AVB_TD3 */
319 [27] = PIN_AVB_TXCREFCLK, /* AVB_TXCREFCLK */
320 [28] = PIN_AVB_MDIO, /* AVB_MDIO */
321 [29] = RCAR_GP_PIN(2, 9), /* AVB_MDC */
322 [30] = RCAR_GP_PIN(2, 10), /* AVB_MAGIC */
323 [31] = RCAR_GP_PIN(2, 11), /* AVB_PHY_INT */
324 } },
325 { PFC_BIAS_REG(0x0404, 0x0444) { /* PUEN1, PUD1 */
326 [0] = RCAR_GP_PIN(2, 12), /* AVB_LINK */
327 [1] = RCAR_GP_PIN(2, 13), /* AVB_AVTP_MATCH_A */
328 [2] = RCAR_GP_PIN(2, 14), /* AVB_AVTP_CAPTURE_A */
329 [3] = RCAR_GP_PIN(2, 0), /* IRQ0 */
330 [4] = RCAR_GP_PIN(2, 1), /* IRQ1 */
331 [5] = RCAR_GP_PIN(2, 2), /* IRQ2 */
332 [6] = RCAR_GP_PIN(2, 3), /* IRQ3 */
333 [7] = RCAR_GP_PIN(2, 4), /* IRQ4 */
334 [8] = RCAR_GP_PIN(2, 5), /* IRQ5 */
335 [9] = RCAR_GP_PIN(2, 6), /* PWM0 */
336 [10] = RCAR_GP_PIN(2, 7), /* PWM1_A */
337 [11] = RCAR_GP_PIN(2, 8), /* PWM2_A */
338 [12] = RCAR_GP_PIN(1, 0), /* A0 */
339 [13] = RCAR_GP_PIN(1, 1), /* A1 */
340 [14] = RCAR_GP_PIN(1, 2), /* A2 */
341 [15] = RCAR_GP_PIN(1, 3), /* A3 */
342 [16] = RCAR_GP_PIN(1, 4), /* A4 */
343 [17] = RCAR_GP_PIN(1, 5), /* A5 */
344 [18] = RCAR_GP_PIN(1, 6), /* A6 */
345 [19] = RCAR_GP_PIN(1, 7), /* A7 */
346 [20] = RCAR_GP_PIN(1, 8), /* A8 */
347 [21] = RCAR_GP_PIN(1, 9), /* A9 */
348 [22] = RCAR_GP_PIN(1, 10), /* A10 */
349 [23] = RCAR_GP_PIN(1, 11), /* A11 */
350 [24] = RCAR_GP_PIN(1, 12), /* A12 */
351 [25] = RCAR_GP_PIN(1, 13), /* A13 */
352 [26] = RCAR_GP_PIN(1, 14), /* A14 */
353 [27] = RCAR_GP_PIN(1, 15), /* A15 */
354 [28] = RCAR_GP_PIN(1, 16), /* A16 */
355 [29] = RCAR_GP_PIN(1, 17), /* A17 */
356 [30] = RCAR_GP_PIN(1, 18), /* A18 */
357 [31] = RCAR_GP_PIN(1, 19), /* A19 */
358 } },
359 { PFC_BIAS_REG(0x0408, 0x0448) { /* PUEN2, PUD2 */
360 [0] = RCAR_GP_PIN(1, 28), /* CLKOUT */
361 [1] = RCAR_GP_PIN(1, 20), /* CS0_N */
362 [2] = RCAR_GP_PIN(1, 21), /* CS1_N */
363 [3] = RCAR_GP_PIN(1, 22), /* BS_N */
364 [4] = RCAR_GP_PIN(1, 23), /* RD_N */
365 [5] = RCAR_GP_PIN(1, 24), /* RD_WR_N */
366 [6] = RCAR_GP_PIN(1, 25), /* WE0_N */
367 [7] = RCAR_GP_PIN(1, 26), /* WE1_N */
368 [8] = RCAR_GP_PIN(1, 27), /* EX_WAIT0_A */
369 [9] = PIN_PRESETOUT_N, /* PRESETOUT# */
370 [10] = RCAR_GP_PIN(0, 0), /* D0 */
371 [11] = RCAR_GP_PIN(0, 1), /* D1 */
372 [12] = RCAR_GP_PIN(0, 2), /* D2 */
373 [13] = RCAR_GP_PIN(0, 3), /* D3 */
374 [14] = RCAR_GP_PIN(0, 4), /* D4 */
375 [15] = RCAR_GP_PIN(0, 5), /* D5 */
376 [16] = RCAR_GP_PIN(0, 6), /* D6 */
377 [17] = RCAR_GP_PIN(0, 7), /* D7 */
378 [18] = RCAR_GP_PIN(0, 8), /* D8 */
379 [19] = RCAR_GP_PIN(0, 9), /* D9 */
380 [20] = RCAR_GP_PIN(0, 10), /* D10 */
381 [21] = RCAR_GP_PIN(0, 11), /* D11 */
382 [22] = RCAR_GP_PIN(0, 12), /* D12 */
383 [23] = RCAR_GP_PIN(0, 13), /* D13 */
384 [24] = RCAR_GP_PIN(0, 14), /* D14 */
385 [25] = RCAR_GP_PIN(0, 15), /* D15 */
386 [26] = RCAR_GP_PIN(7, 0), /* AVS1 */
387 [27] = RCAR_GP_PIN(7, 1), /* AVS2 */
388 [28] = RCAR_GP_PIN(7, 2), /* GP7_02 */
389 [29] = RCAR_GP_PIN(7, 3), /* GP7_03 */
390 [30] = PIN_DU_DOTCLKIN0, /* DU_DOTCLKIN0 */
391 [31] = PIN_DU_DOTCLKIN1, /* DU_DOTCLKIN1 */
392 } },
393 { PFC_BIAS_REG(0x040c, 0x044c) { /* PUEN3, PUD3 */
394 [0] = PIN_DU_DOTCLKIN2, /* DU_DOTCLKIN2 */
395 [1] = PIN_DU_DOTCLKIN3, /* DU_DOTCLKIN3 */
396 [2] = PIN_FSCLKST_N, /* FSCLKST# */
397 [3] = PIN_EXTALR, /* EXTALR*/
398 [4] = PIN_TRST_N, /* TRST# */
399 [5] = PIN_TCK, /* TCK */
400 [6] = PIN_TMS, /* TMS */
401 [7] = PIN_TDI, /* TDI */
402 [8] = PIN_NONE,
403 [9] = PIN_ASEBRK, /* ASEBRK */
404 [10] = RCAR_GP_PIN(3, 0), /* SD0_CLK */
405 [11] = RCAR_GP_PIN(3, 1), /* SD0_CMD */
406 [12] = RCAR_GP_PIN(3, 2), /* SD0_DAT0 */
407 [13] = RCAR_GP_PIN(3, 3), /* SD0_DAT1 */
408 [14] = RCAR_GP_PIN(3, 4), /* SD0_DAT2 */
409 [15] = RCAR_GP_PIN(3, 5), /* SD0_DAT3 */
410 [16] = RCAR_GP_PIN(3, 6), /* SD1_CLK */
411 [17] = RCAR_GP_PIN(3, 7), /* SD1_CMD */
412 [18] = RCAR_GP_PIN(3, 8), /* SD1_DAT0 */
413 [19] = RCAR_GP_PIN(3, 9), /* SD1_DAT1 */
414 [20] = RCAR_GP_PIN(3, 10), /* SD1_DAT2 */
415 [21] = RCAR_GP_PIN(3, 11), /* SD1_DAT3 */
416 [22] = RCAR_GP_PIN(4, 0), /* SD2_CLK */
417 [23] = RCAR_GP_PIN(4, 1), /* SD2_CMD */
418 [24] = RCAR_GP_PIN(4, 2), /* SD2_DAT0 */
419 [25] = RCAR_GP_PIN(4, 3), /* SD2_DAT1 */
420 [26] = RCAR_GP_PIN(4, 4), /* SD2_DAT2 */
421 [27] = RCAR_GP_PIN(4, 5), /* SD2_DAT3 */
422 [28] = RCAR_GP_PIN(4, 6), /* SD2_DS */
423 [29] = RCAR_GP_PIN(4, 7), /* SD3_CLK */
424 [30] = RCAR_GP_PIN(4, 8), /* SD3_CMD */
425 [31] = RCAR_GP_PIN(4, 9), /* SD3_DAT0 */
426 } },
427 { PFC_BIAS_REG(0x0410, 0x0450) { /* PUEN4, PUD4 */
428 [0] = RCAR_GP_PIN(4, 10), /* SD3_DAT1 */
429 [1] = RCAR_GP_PIN(4, 11), /* SD3_DAT2 */
430 [2] = RCAR_GP_PIN(4, 12), /* SD3_DAT3 */
431 [3] = RCAR_GP_PIN(4, 13), /* SD3_DAT4 */
432 [4] = RCAR_GP_PIN(4, 14), /* SD3_DAT5 */
433 [5] = RCAR_GP_PIN(4, 15), /* SD3_DAT6 */
434 [6] = RCAR_GP_PIN(4, 16), /* SD3_DAT7 */
435 [7] = RCAR_GP_PIN(4, 17), /* SD3_DS */
436 [8] = RCAR_GP_PIN(3, 12), /* SD0_CD */
437 [9] = RCAR_GP_PIN(3, 13), /* SD0_WP */
438 [10] = RCAR_GP_PIN(3, 14), /* SD1_CD */
439 [11] = RCAR_GP_PIN(3, 15), /* SD1_WP */
440 [12] = RCAR_GP_PIN(5, 0), /* SCK0 */
441 [13] = RCAR_GP_PIN(5, 1), /* RX0 */
442 [14] = RCAR_GP_PIN(5, 2), /* TX0 */
443 [15] = RCAR_GP_PIN(5, 3), /* CTS0_N */
444 [16] = RCAR_GP_PIN(5, 4), /* RTS0_N */
445 [17] = RCAR_GP_PIN(5, 5), /* RX1_A */
446 [18] = RCAR_GP_PIN(5, 6), /* TX1_A */
447 [19] = RCAR_GP_PIN(5, 7), /* CTS1_N */
448 [20] = RCAR_GP_PIN(5, 8), /* RTS1_N */
449 [21] = RCAR_GP_PIN(5, 9), /* SCK2 */
450 [22] = RCAR_GP_PIN(5, 10), /* TX2_A */
451 [23] = RCAR_GP_PIN(5, 11), /* RX2_A */
452 [24] = RCAR_GP_PIN(5, 12), /* HSCK0 */
453 [25] = RCAR_GP_PIN(5, 13), /* HRX0 */
454 [26] = RCAR_GP_PIN(5, 14), /* HTX0 */
455 [27] = RCAR_GP_PIN(5, 15), /* HCTS0_N */
456 [28] = RCAR_GP_PIN(5, 16), /* HRTS0_N */
457 [29] = RCAR_GP_PIN(5, 17), /* MSIOF0_SCK */
458 [30] = RCAR_GP_PIN(5, 18), /* MSIOF0_SYNC */
459 [31] = RCAR_GP_PIN(5, 19), /* MSIOF0_SS1 */
460 } },
461 { PFC_BIAS_REG(0x0414, 0x0454) { /* PUEN5, PUD5 */
462 [0] = RCAR_GP_PIN(5, 20), /* MSIOF0_TXD */
463 [1] = RCAR_GP_PIN(5, 21), /* MSIOF0_SS2 */
464 [2] = RCAR_GP_PIN(5, 22), /* MSIOF0_RXD */
465 [3] = RCAR_GP_PIN(5, 23), /* MLB_CLK */
466 [4] = RCAR_GP_PIN(5, 24), /* MLB_SIG */
467 [5] = RCAR_GP_PIN(5, 25), /* MLB_DAT */
468 [6] = PIN_MLB_REF, /* MLB_REF */
469 [7] = RCAR_GP_PIN(6, 0), /* SSI_SCK01239 */
470 [8] = RCAR_GP_PIN(6, 1), /* SSI_WS01239 */
471 [9] = RCAR_GP_PIN(6, 2), /* SSI_SDATA0 */
472 [10] = RCAR_GP_PIN(6, 3), /* SSI_SDATA1_A */
473 [11] = RCAR_GP_PIN(6, 4), /* SSI_SDATA2_A */
474 [12] = RCAR_GP_PIN(6, 5), /* SSI_SCK349 */
475 [13] = RCAR_GP_PIN(6, 6), /* SSI_WS349 */
476 [14] = RCAR_GP_PIN(6, 7), /* SSI_SDATA3 */
477 [15] = RCAR_GP_PIN(6, 8), /* SSI_SCK4 */
478 [16] = RCAR_GP_PIN(6, 9), /* SSI_WS4 */
479 [17] = RCAR_GP_PIN(6, 10), /* SSI_SDATA4 */
480 [18] = RCAR_GP_PIN(6, 11), /* SSI_SCK5 */
481 [19] = RCAR_GP_PIN(6, 12), /* SSI_WS5 */
482 [20] = RCAR_GP_PIN(6, 13), /* SSI_SDATA5 */
483 [21] = RCAR_GP_PIN(6, 14), /* SSI_SCK6 */
484 [22] = RCAR_GP_PIN(6, 15), /* SSI_WS6 */
485 [23] = RCAR_GP_PIN(6, 16), /* SSI_SDATA6 */
486 [24] = RCAR_GP_PIN(6, 17), /* SSI_SCK78 */
487 [25] = RCAR_GP_PIN(6, 18), /* SSI_WS78 */
488 [26] = RCAR_GP_PIN(6, 19), /* SSI_SDATA7 */
489 [27] = RCAR_GP_PIN(6, 20), /* SSI_SDATA8 */
490 [28] = RCAR_GP_PIN(6, 21), /* SSI_SDATA9_A */
491 [29] = RCAR_GP_PIN(6, 22), /* AUDIO_CLKA_A */
492 [30] = RCAR_GP_PIN(6, 23), /* AUDIO_CLKB_B */
493 [31] = RCAR_GP_PIN(6, 24), /* USB0_PWEN */
494 } },
495 { PFC_BIAS_REG(0x0418, 0x0458) { /* PUEN6, PUD6 */
496 [0] = RCAR_GP_PIN(6, 25), /* USB0_OVC */
497 [1] = RCAR_GP_PIN(6, 26), /* USB1_PWEN */
498 [2] = RCAR_GP_PIN(6, 27), /* USB1_OVC */
499 [3] = RCAR_GP_PIN(6, 28), /* USB30_PWEN */
500 [4] = RCAR_GP_PIN(6, 29), /* USB30_OVC */
501 [5] = RCAR_GP_PIN(6, 30), /* USB2_CH3_PWEN */
502 [6] = RCAR_GP_PIN(6, 31), /* USB2_CH3_OVC */
503 [7] = PIN_NONE,
504 [8] = PIN_NONE,
505 [9] = PIN_NONE,
506 [10] = PIN_NONE,
507 [11] = PIN_NONE,
508 [12] = PIN_NONE,
509 [13] = PIN_NONE,
510 [14] = PIN_NONE,
511 [15] = PIN_NONE,
512 [16] = PIN_NONE,
513 [17] = PIN_NONE,
514 [18] = PIN_NONE,
515 [19] = PIN_NONE,
516 [20] = PIN_NONE,
517 [21] = PIN_NONE,
518 [22] = PIN_NONE,
519 [23] = PIN_NONE,
520 [24] = PIN_NONE,
521 [25] = PIN_NONE,
522 [26] = PIN_NONE,
523 [27] = PIN_NONE,
524 [28] = PIN_NONE,
525 [29] = PIN_NONE,
526 [30] = PIN_NONE,
527 [31] = PIN_NONE,
528 } },
529 { /* sentinel */ },
530 };
pfc_rcar_get_bias_regs(void)531 const struct pfc_bias_reg *pfc_rcar_get_bias_regs(void)
532 {
533 return pfc_bias_regs;
534 }
pfc_rcar_get_drive_regs(void)535 const struct pfc_drive_reg *pfc_rcar_get_drive_regs(void)
536 {
537 return pfc_drive_regs;
538 }
539
