1 /* 2 * Copyright (c) 2020 Antmicro <www.antmicro.com> 3 * 4 * SPDX-License-Identifier: Apache-2.0 5 */ 6 7 #include <zephyr/kernel.h> 8 #include <zephyr/init.h> 9 #include <soc.h> 10 #include <soc_pinmap.h> 11 #include <cmsis_core.h> 12 eos_s3_lock_enable(void)13void eos_s3_lock_enable(void) 14 { 15 MISC_CTRL->LOCK_KEY_CTRL = MISC_LOCK_KEY; 16 } 17 eos_s3_lock_disable(void)18void eos_s3_lock_disable(void) 19 { 20 MISC_CTRL->LOCK_KEY_CTRL = 1; 21 } 22 eos_s3_cru_init(void)23static void eos_s3_cru_init(void) 24 { 25 /* Set desired frequency */ 26 AIP->OSC_CTRL_0 |= AIP_OSC_CTRL_EN; 27 AIP->OSC_CTRL_0 &= ~AIP_OSC_CTRL_FRE_SEL; 28 OSC_SET_FREQ_INC(CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC); 29 30 while (!OSC_CLK_LOCKED()) { 31 ; 32 } 33 34 /* Enable all clocks for every domain */ 35 CRU->CLK_DIVIDER_CLK_GATING = (CLK_DIVIDER_A_CG | CLK_DIVIDER_B_CG 36 | CLK_DIVIDER_C_CG | CLK_DIVIDER_D_CG | CLK_DIVIDER_F_CG 37 | CLK_DIVIDER_G_CG | CLK_DIVIDER_H_CG | CLK_DIVIDER_I_CG 38 | CLK_DIVIDER_J_CG); 39 40 /* Turn off divisor for A0 domain */ 41 CRU->CLK_CTRL_A_0 = 0; 42 43 /* Enable UART, WDT and TIMER peripherals */ 44 CRU->C11_CLK_GATE = C11_CLK_GATE_PATH_0_ON; 45 46 /* Set divider for domain C11 to ~ 5.12MHz */ 47 CRU->CLK_CTRL_D_0 = (CLK_CTRL_CLK_DIVIDER_ENABLE | 48 CLK_CTRL_CLK_DIVIDER_RATIO_12); 49 } 50 51 52 eos_s3_init(void)53static int eos_s3_init(void) 54 { 55 /* Clocks setup */ 56 eos_s3_lock_enable(); 57 eos_s3_cru_init(); 58 eos_s3_lock_disable(); 59 60 SCnSCB->ACTLR |= SCnSCB_ACTLR_DISDEFWBUF_Msk; 61 62 /* Clear all interrupts */ 63 INTR_CTRL->OTHER_INTR = 0xFFFFFF; 64 65 /* Enable UART interrupt */ 66 INTR_CTRL->OTHER_INTR_EN_M4 = UART_INTR_EN_M4; 67 68 return 0; 69 } 70 71 SYS_INIT(eos_s3_init, PRE_KERNEL_1, 0); 72
