1 /*
2  * Copyright 2023 NXP
3  *
4  * SPDX-License-Identifier: Apache-2.0
5  */
6 
7 #include <zephyr/devicetree.h>
8 #include <zephyr/linker/devicetree_regions.h>
9 #include <zephyr/arch/arm/cortex_m/arm_mpu_mem_cfg.h>
10 
11 #if !defined(CONFIG_XIP)
12 extern char _rom_attr[];
13 #endif
14 
15 static struct arm_mpu_region mpu_regions[] = {
16 
17 	/* Keep before CODE region so it can be overlapped by SRAM CODE in non-XIP systems */
18 	{
19 		.name = "SRAM",
20 		.base = CONFIG_SRAM_BASE_ADDRESS,
21 		.attr = REGION_RAM_ATTR(REGION_SRAM_SIZE),
22 	},
23 
24 #ifdef CONFIG_XIP
25 	{
26 		.name = "FLASH",
27 		.base = CONFIG_FLASH_BASE_ADDRESS,
28 		.attr = REGION_FLASH_ATTR(REGION_FLASH_SIZE),
29 	},
30 #else
31 	/* Run from SRAM */
32 	{
33 		.name = "CODE",
34 		.base = CONFIG_SRAM_BASE_ADDRESS,
35 		.attr = {(uint32_t)_rom_attr},
36 	},
37 #endif
38 };
39 
40 const struct arm_mpu_config mpu_config = {
41 	.num_regions = ARRAY_SIZE(mpu_regions),
42 	.mpu_regions = mpu_regions,
43 };
44