1# i.MX RT series 2 3# Copyright (c) 2017-2021, NXP 4# SPDX-License-Identifier: Apache-2.0 5 6choice 7 prompt "i.MX RT Selection" 8 depends on SOC_SERIES_IMX_RT 9 10config SOC_MIMXRT1011 11 bool "SOC_MIMXRT1011" 12 select SOC_SERIES_IMX_RT10XX 13 select HAS_MCUX 14 select HAS_MCUX_CACHE 15 select HAS_MCUX_12B1MSPS_SAR 16 select HAS_MCUX_CCM 17 select HAS_MCUX_FLEXSPI 18 select HAS_MCUX_IGPIO 19 select HAS_MCUX_LPI2C 20 select HAS_MCUX_LPSPI 21 select HAS_MCUX_LPUART 22 select HAS_MCUX_GPT 23 select HAS_MCUX_TRNG 24 select CPU_HAS_ARM_MPU 25 select INIT_ENET_PLL 26 select HAS_MCUX_USB_EHCI 27 select HAS_MCUX_EDMA 28 select HAS_MCUX_GPC 29 select HAS_MCUX_DCDC 30 select HAS_MCUX_PMU 31 select HAS_MCUX_IOMUXC 32 select HAS_SWO 33 34config SOC_MIMXRT1015 35 bool "SOC_MIMXRT1015" 36 select SOC_SERIES_IMX_RT10XX 37 select HAS_MCUX 38 select HAS_MCUX_CACHE 39 select HAS_MCUX_12B1MSPS_SAR 40 select HAS_MCUX_CCM 41 select HAS_MCUX_FLEXSPI 42 select HAS_MCUX_IGPIO 43 select HAS_MCUX_LPI2C 44 select HAS_MCUX_LPSPI 45 select HAS_MCUX_LPUART 46 select HAS_MCUX_GPT 47 select HAS_MCUX_TRNG 48 select CPU_HAS_FPU_DOUBLE_PRECISION 49 select CPU_HAS_ARM_MPU 50 select INIT_ENET_PLL 51 select HAS_MCUX_USB_EHCI 52 select HAS_MCUX_EDMA 53 select HAS_MCUX_GPC 54 select HAS_MCUX_DCDC 55 select HAS_MCUX_PMU 56 select HAS_MCUX_IOMUXC 57 select HAS_SWO 58 59config SOC_MIMXRT1021 60 bool "SOC_MIMXRT1021" 61 select SOC_SERIES_IMX_RT10XX 62 select HAS_MCUX 63 select HAS_MCUX_CACHE 64 select HAS_MCUX_12B1MSPS_SAR 65 select HAS_MCUX_CCM 66 select HAS_MCUX_ENET 67 select HAS_MCUX_FLEXSPI 68 select HAS_MCUX_IGPIO 69 select HAS_MCUX_LPI2C 70 select HAS_MCUX_LPSPI 71 select HAS_MCUX_LPUART 72 select HAS_MCUX_GPT 73 select HAS_MCUX_SEMC 74 select HAS_MCUX_TRNG 75 select CPU_HAS_FPU_DOUBLE_PRECISION 76 select CPU_HAS_ARM_MPU 77 select INIT_ENET_PLL 78 select HAS_MCUX_USB_EHCI 79 select HAS_MCUX_USDHC1 80 select HAS_MCUX_USDHC2 81 select HAS_MCUX_EDMA 82 select HAS_MCUX_FLEXCAN 83 select HAS_MCUX_PWM 84 select HAS_MCUX_GPC 85 select HAS_MCUX_DCDC 86 select HAS_MCUX_PMU 87 select HAS_MCUX_IOMUXC 88 select HAS_SWO 89 90config SOC_MIMXRT1024 91 bool "SOC_MIMXRT1024" 92 select SOC_SERIES_IMX_RT10XX 93 select HAS_MCUX 94 select HAS_MCUX_CACHE 95 select HAS_MCUX_12B1MSPS_SAR 96 select HAS_MCUX_CCM 97 select HAS_MCUX_ENET 98 select HAS_MCUX_FLEXSPI 99 select HAS_MCUX_IGPIO 100 select HAS_MCUX_LPI2C 101 select HAS_MCUX_LPSPI 102 select HAS_MCUX_LPUART 103 select HAS_MCUX_GPT 104 select HAS_MCUX_SEMC 105 select HAS_MCUX_TRNG 106 select CPU_HAS_FPU_DOUBLE_PRECISION 107 select CPU_HAS_ARM_MPU 108 select INIT_ENET_PLL 109 select HAS_MCUX_USB_EHCI 110 select HAS_MCUX_USDHC1 111 select HAS_MCUX_USDHC2 112 select HAS_MCUX_EDMA 113 select HAS_MCUX_FLEXCAN 114 select HAS_MCUX_SRC 115 select HAS_MCUX_GPC 116 select HAS_MCUX_DCDC 117 select HAS_MCUX_PMU 118 select HAS_MCUX_IOMUXC 119 select HAS_SWO 120 121config SOC_MIMXRT1042 122 bool "SOC_MIMXRT1042" 123 select SOC_SERIES_IMX_RT10XX 124 select HAS_MCUX 125 select HAS_MCUX_CACHE 126 select HAS_MCUX_FLEXSPI 127 select HAS_MCUX_SEMC 128 select HAS_MCUX_IGPIO 129 select CPU_HAS_FPU_DOUBLE_PRECISION 130 select CPU_HAS_ARM_MPU 131 select INIT_ARM_PLL 132 select HAS_MCUX_EDMA 133 select HAS_MCUX_GPC 134 select HAS_MCUX_DCDC 135 select HAS_MCUX_PMU 136 select HAS_MCUX_IOMUXC 137 select HAS_SWO 138 139config SOC_MIMXRT1051 140 bool "SOC_MIMXRT1051" 141 select SOC_SERIES_IMX_RT10XX 142 select HAS_MCUX 143 select HAS_MCUX_CACHE 144 select HAS_MCUX_12B1MSPS_SAR 145 select HAS_MCUX_CCM 146 select HAS_MCUX_ENET 147 select HAS_MCUX_FLEXSPI 148 select HAS_MCUX_IGPIO 149 select HAS_MCUX_LPI2C 150 select HAS_MCUX_LPSPI 151 select HAS_MCUX_LPUART 152 select HAS_MCUX_GPT 153 select HAS_MCUX_SEMC 154 select HAS_MCUX_TRNG 155 select CPU_HAS_FPU_DOUBLE_PRECISION 156 select CPU_HAS_ARM_MPU 157 select INIT_ARM_PLL 158 select HAS_MCUX_USB_EHCI 159 select HAS_MCUX_USDHC1 160 select HAS_MCUX_USDHC2 161 select HAS_MCUX_CSI 162 select HAS_MCUX_EDMA 163 select HAS_MCUX_FLEXCAN 164 select HAS_MCUX_GPC 165 select HAS_MCUX_DCDC 166 select HAS_MCUX_PMU 167 select HAS_MCUX_IOMUXC 168 select HAS_SWO 169 170config SOC_MIMXRT1052 171 bool "SOC_MIMXRT1052" 172 select SOC_SERIES_IMX_RT10XX 173 select HAS_MCUX 174 select HAS_MCUX_CACHE 175 select HAS_MCUX_12B1MSPS_SAR 176 select HAS_MCUX_CCM 177 select HAS_MCUX_ELCDIF 178 select HAS_MCUX_ENET 179 select HAS_MCUX_FLEXSPI 180 select HAS_MCUX_IGPIO 181 select HAS_MCUX_LPI2C 182 select HAS_MCUX_LPSPI 183 select HAS_MCUX_LPUART 184 select HAS_MCUX_GPT 185 select HAS_MCUX_SEMC 186 select HAS_MCUX_TRNG 187 select CPU_HAS_FPU_DOUBLE_PRECISION 188 select CPU_HAS_ARM_MPU 189 select INIT_ARM_PLL 190 select INIT_VIDEO_PLL if DISPLAY_MCUX_ELCDIF 191 select INIT_ENET_PLL if NET_L2_ETHERNET && ETH_DRIVER 192 select HAS_MCUX_USB_EHCI 193 select HAS_MCUX_USDHC1 194 select HAS_MCUX_USDHC2 195 select HAS_MCUX_CSI 196 select HAS_MCUX_EDMA 197 select HAS_MCUX_FLEXCAN 198 select HAS_MCUX_PWM 199 select HAS_MCUX_GPC 200 select HAS_MCUX_DCDC 201 select HAS_MCUX_PMU 202 select HAS_MCUX_IOMUXC 203 select HAS_MCUX_SRC 204 select HAS_SWO 205 select HAS_MCUX_XBARA 206 207config SOC_MIMXRT1061 208 bool "SOC_MIMXRT1061" 209 select SOC_SERIES_IMX_RT10XX 210 select HAS_MCUX 211 select HAS_MCUX_CACHE 212 select HAS_MCUX_12B1MSPS_SAR 213 select HAS_MCUX_CCM 214 select HAS_MCUX_ENET 215 select HAS_MCUX_FLEXSPI 216 select HAS_MCUX_IGPIO 217 select HAS_MCUX_LPI2C 218 select HAS_MCUX_LPSPI 219 select HAS_MCUX_LPUART 220 select HAS_MCUX_GPT 221 select HAS_MCUX_SEMC 222 select HAS_MCUX_TRNG 223 select CPU_HAS_FPU_DOUBLE_PRECISION 224 select CPU_HAS_ARM_MPU 225 select INIT_ARM_PLL 226 select HAS_MCUX_USB_EHCI 227 select HAS_MCUX_USDHC1 228 select HAS_MCUX_USDHC2 229 select HAS_MCUX_CSI 230 select HAS_MCUX_EDMA 231 select HAS_MCUX_FLEXCAN 232 select HAS_MCUX_GPC 233 select HAS_MCUX_DCDC 234 select HAS_MCUX_PMU 235 select HAS_MCUX_IOMUXC 236 select HAS_SWO 237 238config SOC_MIMXRT1062 239 bool "SOC_MIMXRT1062" 240 select SOC_SERIES_IMX_RT10XX 241 select HAS_MCUX 242 select HAS_MCUX_CACHE 243 select HAS_MCUX_12B1MSPS_SAR 244 select HAS_MCUX_CCM 245 select HAS_MCUX_ELCDIF 246 select HAS_MCUX_ENET 247 select HAS_MCUX_FLEXSPI 248 select HAS_MCUX_PWM 249 select HAS_MCUX_IGPIO 250 select HAS_MCUX_LPI2C 251 select HAS_MCUX_LPSPI 252 select HAS_MCUX_LPUART 253 select HAS_MCUX_GPT 254 select HAS_MCUX_QTMR 255 select HAS_MCUX_SEMC 256 select HAS_MCUX_SNVS 257 select HAS_MCUX_TRNG 258 select CPU_HAS_FPU_DOUBLE_PRECISION 259 select CPU_HAS_ARM_MPU 260 select INIT_ARM_PLL 261 select INIT_VIDEO_PLL if DISPLAY_MCUX_ELCDIF 262 select INIT_ENET_PLL if NET_L2_ETHERNET && ETH_DRIVER 263 select HAS_MCUX_USB_EHCI 264 select HAS_MCUX_USDHC1 265 select HAS_MCUX_USDHC2 266 select HAS_MCUX_CSI 267 select HAS_MCUX_EDMA 268 select HAS_MCUX_FLEXCAN 269 select HAS_MCUX_I2S 270 select HAS_MCUX_GPC 271 select HAS_MCUX_DCDC 272 select HAS_MCUX_PMU 273 select HAS_MCUX_IOMUXC 274 select HAS_MCUX_ADC_ETC 275 select HAS_MCUX_SRC 276 select HAS_SWO 277 select HAS_MCUX_XBARA 278 279config SOC_MIMXRT1064 280 bool "SOC_MIMXRT1064" 281 select SOC_SERIES_IMX_RT10XX 282 select HAS_MCUX 283 select HAS_MCUX_CACHE 284 select HAS_MCUX_12B1MSPS_SAR 285 select HAS_MCUX_CCM 286 select HAS_MCUX_ELCDIF 287 select HAS_MCUX_ENET 288 select HAS_MCUX_FLEXSPI 289 select HAS_MCUX_PWM 290 select HAS_MCUX_IGPIO 291 select HAS_MCUX_LPI2C 292 select HAS_MCUX_LPSPI 293 select HAS_MCUX_LPUART 294 select HAS_MCUX_GPT 295 select HAS_MCUX_QTMR 296 select HAS_MCUX_SEMC 297 select HAS_MCUX_SNVS 298 select HAS_MCUX_SRC 299 select HAS_MCUX_TRNG 300 select CPU_HAS_FPU_DOUBLE_PRECISION 301 select CPU_HAS_ARM_MPU 302 select INIT_ARM_PLL 303 select INIT_VIDEO_PLL if DISPLAY_MCUX_ELCDIF 304 select INIT_ENET_PLL if NET_L2_ETHERNET && ETH_DRIVER 305 select HAS_MCUX_USB_EHCI 306 select HAS_MCUX_USDHC1 307 select HAS_MCUX_USDHC2 308 select HAS_MCUX_CSI 309 select HAS_MCUX_EDMA 310 select HAS_MCUX_FLEXCAN 311 select HAS_MCUX_GPC 312 select HAS_MCUX_DCDC 313 select HAS_MCUX_PMU 314 select HAS_MCUX_IOMUXC 315 select HAS_SWO 316 317config SOC_MIMXRT1176_CM7 318 bool "SOC_MIMXRT1176_CM7" 319 select CPU_CORTEX_M7 320 select CPU_CORTEX_M_HAS_DWT 321 select SOC_SERIES_IMX_RT11XX 322 select HAS_MCUX_CACHE 323 select HAS_MCUX 324 select HAS_MCUX_SEMC 325 select HAS_MCUX_CCM_REV2 326 select HAS_MCUX_IGPIO 327 select HAS_MCUX_LPI2C 328 select HAS_MCUX_LPSPI 329 select HAS_MCUX_LPADC 330 select HAS_MCUX_LPUART 331 select HAS_MCUX_ELCDIF 332 select HAS_MCUX_MIPI_DSI 333 select HAS_MCUX_GPT 334 select HAS_MCUX_FLEXSPI 335 select HAS_MCUX_FLEXCAN 336 select CPU_HAS_ARM_MPU 337 select INIT_ARM_PLL 338 select INIT_ENET_PLL if NET_L2_ETHERNET && ETH_DRIVER 339 select INIT_VIDEO_PLL 340 select HAS_MCUX_EDMA 341 select CPU_HAS_FPU_DOUBLE_PRECISION 342 select ADJUST_DCDC 343 select BYPASS_LDO_LPSR 344 select ADJUST_LDO 345 select HAS_MCUX_PWM 346 select HAS_MCUX_USDHC1 347 select HAS_MCUX_USDHC2 348 select HAS_MCUX_ENET 349 select HAS_MCUX_GPC 350 select HAS_MCUX_I2S 351 select HAS_MCUX_USB_EHCI 352 select HAS_MCUX_ACMP 353 select HAS_MCUX_SRC_V2 354 select HAS_MCUX_IOMUXC 355 select HAS_MCUX_XBARA 356 select HAS_SWO 357 358config SOC_MIMXRT1176_CM4 359 bool "SOC_MIMXRT1176_CM4" 360 select CPU_CORTEX_M4 361 select SOC_SERIES_IMX_RT11XX 362 select HAS_MCUX_CACHE 363 select HAS_MCUX 364 select HAS_MCUX_SEMC 365 select HAS_MCUX_CCM_REV2 366 select HAS_MCUX_IGPIO 367 select HAS_MCUX_LPI2C 368 select HAS_MCUX_LPSPI 369 select HAS_MCUX_FLEXSPI 370 select HAS_MCUX_LPUART 371 select HAS_MCUX_GPT 372 select CPU_HAS_ARM_MPU 373 select INIT_ARM_PLL 374 select INIT_ENET_PLL if NET_L2_ETHERNET && ETH_DRIVER 375 select INIT_VIDEO_PLL 376 select HAS_MCUX_EDMA 377 select HAS_MCUX_PWM 378 select HAS_MCUX_USDHC1 379 select HAS_MCUX_USDHC2 380 select HAS_MCUX_ENET 381 select HAS_MCUX_GPC 382 select HAS_MCUX_I2S 383 select HAS_MCUX_ACMP 384 select HAS_MCUX_SRC_V2 385 select HAS_MCUX_IOMUXC 386 select HAS_SWO 387 388config SOC_MIMXRT1166_CM7 389 bool "SOC_MIMXRT1166_CM7" 390 select CPU_CORTEX_M7 391 select CPU_CORTEX_M_HAS_DWT 392 select SOC_SERIES_IMX_RT11XX 393 select HAS_MCUX_CACHE 394 select HAS_MCUX 395 select HAS_MCUX_SEMC 396 select HAS_MCUX_CCM_REV2 397 select HAS_MCUX_IGPIO 398 select HAS_MCUX_LPI2C 399 select HAS_MCUX_LPSPI 400 select HAS_MCUX_LPADC 401 select HAS_MCUX_LPUART 402 select HAS_MCUX_FLEXSPI 403 select HAS_MCUX_GPT 404 select HAS_MCUX_FLEXCAN 405 select CPU_HAS_ARM_MPU 406 select INIT_ARM_PLL 407 select INIT_ENET_PLL if NET_L2_ETHERNET && ETH_DRIVER 408 select INIT_VIDEO_PLL 409 select HAS_MCUX_EDMA 410 select CPU_HAS_FPU_DOUBLE_PRECISION 411 select ADJUST_DCDC 412 select BYPASS_LDO_LPSR 413 select ADJUST_LDO 414 select HAS_MCUX_PWM 415 select HAS_MCUX_USDHC1 416 select HAS_MCUX_USDHC2 417 select HAS_MCUX_ENET 418 select HAS_MCUX_GPC 419 select HAS_MCUX_USB_EHCI 420 select HAS_MCUX_SRC_V2 421 select HAS_MCUX_IOMUXC 422 select HAS_SWO 423 424 425config SOC_MIMXRT1166_CM4 426 bool "SOC_MIMXRT1166_CM4" 427 select CPU_CORTEX_M4 428 select SOC_SERIES_IMX_RT11XX 429 select HAS_MCUX_CACHE 430 select HAS_MCUX 431 select HAS_MCUX_SEMC 432 select HAS_MCUX_CCM_REV2 433 select HAS_MCUX_IGPIO 434 select HAS_MCUX_LPI2C 435 select HAS_MCUX_LPSPI 436 select HAS_MCUX_LPUART 437 select HAS_MCUX_FLEXSPI 438 select HAS_MCUX_GPT 439 select CPU_HAS_ARM_MPU 440 select INIT_ARM_PLL 441 select INIT_ENET_PLL if NET_L2_ETHERNET && ETH_DRIVER 442 select INIT_VIDEO_PLL 443 select HAS_MCUX_EDMA 444 select HAS_MCUX_PWM 445 select HAS_MCUX_USDHC1 446 select HAS_MCUX_USDHC2 447 select HAS_MCUX_ENET 448 select HAS_MCUX_GPC 449 select HAS_MCUX_SRC_V2 450 select HAS_MCUX_IOMUXC 451 select HAS_SWO 452 453endchoice 454 455if SOC_SERIES_IMX_RT 456 457config SOC_PART_NUMBER_MIMXRT1011CAE4A 458 bool 459 460config SOC_PART_NUMBER_MIMXRT1011DAE5A 461 bool 462 463config SOC_PART_NUMBER_MIMXRT1015CAF4A 464 bool 465 466config SOC_PART_NUMBER_MIMXRT1015DAF5A 467 bool 468 469config SOC_PART_NUMBER_MIMXRT1021CAF4A 470 bool 471 472config SOC_PART_NUMBER_MIMXRT1021CAG4A 473 bool 474 475config SOC_PART_NUMBER_MIMXRT1021DAF5A 476 bool 477 478config SOC_PART_NUMBER_MIMXRT1021DAG5A 479 bool 480 481config SOC_PART_NUMBER_MIMXRT1024CAG4A 482 bool 483 484config SOC_PART_NUMBER_MIMXRT1024DAG5A 485 bool 486 487config SOC_PART_NUMBER_MIMXRT1041DFP6B 488 bool 489 490config SOC_PART_NUMBER_MIMXRT1041DJM6B 491 bool 492 493config SOC_PART_NUMBER_MIMXRT1041XFP5B 494 bool 495 496config SOC_PART_NUMBER_MIMXRT1041XJM5B 497 bool 498 499config SOC_PART_NUMBER_MIMXRT1042DFP6B 500 bool 501 502config SOC_PART_NUMBER_MIMXRT1042DJM6B 503 bool 504 505config SOC_PART_NUMBER_MIMXRT1042XFP5B 506 bool 507 508config SOC_PART_NUMBER_MIMXRT1042XJM5B 509 bool 510 511config SOC_PART_NUMBER_MIMXRT1051CVL5A 512 bool 513 514config SOC_PART_NUMBER_MIMXRT1051DVL6A 515 bool 516 517config SOC_PART_NUMBER_MIMXRT1052CVJ5B 518 bool 519 520config SOC_PART_NUMBER_MIMXRT1052CVL5A 521 bool 522 523config SOC_PART_NUMBER_MIMXRT1052CVL5B 524 bool 525 526config SOC_PART_NUMBER_MIMXRT1052DVJ6B 527 bool 528 529config SOC_PART_NUMBER_MIMXRT1052DVL6A 530 bool 531 532config SOC_PART_NUMBER_MIMXRT1052DVL6B 533 bool 534 535config SOC_PART_NUMBER_MIMXRT1061CVL5A 536 bool 537 538config SOC_PART_NUMBER_MIMXRT1061DVL6A 539 bool 540 541config SOC_PART_NUMBER_MIMXRT1062CVJ5A 542 bool 543 544config SOC_PART_NUMBER_MIMXRT1062CVJ5B 545 bool 546 547config SOC_PART_NUMBER_MIMXRT1062CVL5A 548 bool 549 550config SOC_PART_NUMBER_MIMXRT1062DVJ6A 551 bool 552 553config SOC_PART_NUMBER_MIMXRT1062DVL6A 554 bool 555 556config SOC_PART_NUMBER_MIMXRT1064CVL5A 557 bool 558 559config SOC_PART_NUMBER_MIMXRT1064DVL6A 560 bool 561 562config SOC_PART_NUMBER_MIMXRT1166DVM6A 563 bool 564 565config SOC_PART_NUMBER_MIMXRT1176AVM8A 566 bool 567 568config SOC_PART_NUMBER_MIMXRT1176CVM8A 569 bool 570 571config SOC_PART_NUMBER_MIMXRT1176DVMAA 572 bool 573 574config SOC_PART_NUMBER_MIMXRT1175AVM8A 575 bool 576 577config SOC_PART_NUMBER_MIMXRT1175CVM8A 578 bool 579 580config SOC_PART_NUMBER_MIMXRT1175DVMAA 581 bool 582 583config SOC_PART_NUMBER_MIMXRT1173CVM8A 584 bool 585 586config SOC_PART_NUMBER_MIMXRT1172AVM8A 587 bool 588 589config SOC_PART_NUMBER_MIMXRT1172CVM8A 590 bool 591 592config SOC_PART_NUMBER_MIMXRT1172DVMAA 593 bool 594 595config SOC_PART_NUMBER_MIMXRT1171AVM8A 596 bool 597 598config SOC_PART_NUMBER_MIMXRT1171CVM8A 599 bool 600 601config SOC_PART_NUMBER_MIMXRT1171DVMAA 602 bool 603 604config SOC_PART_NUMBER_IMX_RT 605 string 606 default "MIMXRT1011CAE4A" if SOC_PART_NUMBER_MIMXRT1011CAE4A 607 default "MIMXRT1011DAE5A" if SOC_PART_NUMBER_MIMXRT1011DAE5A 608 default "MIMXRT1015CAF4A" if SOC_PART_NUMBER_MIMXRT1015CAF4A 609 default "MIMXRT1015DAF5A" if SOC_PART_NUMBER_MIMXRT1015DAF5A 610 default "MIMXRT1021CAF4A" if SOC_PART_NUMBER_MIMXRT1021CAF4A 611 default "MIMXRT1021CAG4A" if SOC_PART_NUMBER_MIMXRT1021CAG4A 612 default "MIMXRT1021DAF5A" if SOC_PART_NUMBER_MIMXRT1021DAF5A 613 default "MIMXRT1021DAG5A" if SOC_PART_NUMBER_MIMXRT1021DAG5A 614 default "MIMXRT1024CAG4A" if SOC_PART_NUMBER_MIMXRT1024CAG4A 615 default "MIMXRT1024DAG5A" if SOC_PART_NUMBER_MIMXRT1024DAG5A 616 default "MIMXRT1041DFP6B" if SOC_PART_NUMBER_MIMXRT1041DFP6B 617 default "MIMXRT1041DJM6B" if SOC_PART_NUMBER_MIMXRT1041DJM6B 618 default "MIMXRT1041XFP5B" if SOC_PART_NUMBER_MIMXRT1041XFP5B 619 default "MIMXRT1041XJM5B" if SOC_PART_NUMBER_MIMXRT1041XJM5B 620 default "MIMXRT1042DFP6B" if SOC_PART_NUMBER_MIMXRT1042DFP6B 621 default "MIMXRT1042DJM6B" if SOC_PART_NUMBER_MIMXRT1042DJM6B 622 default "MIMXRT1042XFP5B" if SOC_PART_NUMBER_MIMXRT1042XFP5B 623 default "MIMXRT1042XJM5B" if SOC_PART_NUMBER_MIMXRT1042XJM5B 624 default "MIMXRT1051CVL5A" if SOC_PART_NUMBER_MIMXRT1051CVL5A 625 default "MIMXRT1051DVL6A" if SOC_PART_NUMBER_MIMXRT1051DVL6A 626 default "MIMXRT1052CVJ5B" if SOC_PART_NUMBER_MIMXRT1052CVJ5B 627 default "MIMXRT1052CVL5A" if SOC_PART_NUMBER_MIMXRT1052CVL5A 628 default "MIMXRT1052CVL5B" if SOC_PART_NUMBER_MIMXRT1052CVL5B 629 default "MIMXRT1052DVJ6B" if SOC_PART_NUMBER_MIMXRT1052DVJ6B 630 default "MIMXRT1052DVL6A" if SOC_PART_NUMBER_MIMXRT1052DVL6A 631 default "MIMXRT1052DVL6B" if SOC_PART_NUMBER_MIMXRT1052DVL6B 632 default "MIMXRT1061CVL5A" if SOC_PART_NUMBER_MIMXRT1061CVL5A 633 default "MIMXRT1061DVL6A" if SOC_PART_NUMBER_MIMXRT1061DVL6A 634 default "MIMXRT1062CVJ5A" if SOC_PART_NUMBER_MIMXRT1062CVJ5A 635 default "MIMXRT1062CVJ5B" if SOC_PART_NUMBER_MIMXRT1062CVJ5B 636 default "MIMXRT1062CVL5A" if SOC_PART_NUMBER_MIMXRT1062CVL5A 637 default "MIMXRT1062DVJ6A" if SOC_PART_NUMBER_MIMXRT1062DVJ6A 638 default "MIMXRT1062DVL6A" if SOC_PART_NUMBER_MIMXRT1062DVL6A 639 default "MIMXRT1064CVL5A" if SOC_PART_NUMBER_MIMXRT1064CVL5A 640 default "MIMXRT1064DVL6A" if SOC_PART_NUMBER_MIMXRT1064DVL6A 641 default "MIMXRT1176AVM8A" if SOC_PART_NUMBER_MIMXRT1176AVM8A 642 default "MIMXRT1176CVM8A" if SOC_PART_NUMBER_MIMXRT1176CVM8A 643 default "MIMXRT1176DVMAA" if SOC_PART_NUMBER_MIMXRT1176DVMAA 644 default "MIMXRT1166DVM6A" if SOC_PART_NUMBER_MIMXRT1166DVM6A 645 default "MIMXRT1175AVM8A" if SOC_PART_NUMBER_MIMXRT1175AVM8A 646 default "MIMXRT1175CVM8A" if SOC_PART_NUMBER_MIMXRT1175CVM8A 647 default "MIMXRT1175DVMAA" if SOC_PART_NUMBER_MIMXRT1175DVMAA 648 default "MIMXRT1173CVM8A" if SOC_PART_NUMBER_MIMXRT1173CVM8A 649 default "MIMXRT1172AVM8A" if SOC_PART_NUMBER_MIMXRT1172AVM8A 650 default "MIMXRT1172CVM8A" if SOC_PART_NUMBER_MIMXRT1172CVM8A 651 default "MIMXRT1172DVMAA" if SOC_PART_NUMBER_MIMXRT1172DVMAA 652 default "MIMXRT1171AVM8A" if SOC_PART_NUMBER_MIMXRT1171AVM8A 653 default "MIMXRT1171CVM8A" if SOC_PART_NUMBER_MIMXRT1171CVM8A 654 default "MIMXRT1171DVMAA" if SOC_PART_NUMBER_MIMXRT1171DVMAA 655 help 656 This string holds the full part number of the SoC. It is a hidden option 657 that you should not set directly. The part number selection choice defines 658 the default value for this string. 659 660config SOC_SERIES_IMX_RT10XX 661 bool "i.MX RT 10XX Series" 662 select CPU_CORTEX_M7 663 select CPU_CORTEX_M_HAS_DWT 664 select PLATFORM_SPECIFIC_INIT 665 666config SOC_SERIES_IMX_RT11XX 667 bool "i.MX RT 11XX Series" 668 select PLATFORM_SPECIFIC_INIT 669 670config INIT_ARM_PLL 671 bool "Initialize ARM PLL" 672 673config INIT_VIDEO_PLL 674 bool "Initialize Video PLL" 675 676config INIT_ENET_PLL 677 bool 678 help 679 If y, the Ethernet PLL is initialized. Always enabled on e.g. 680 MIMXRT1021 - see commit 17f4d6bec7 ("soc: nxp_imx: fix ENET_PLL selection 681 for MIMXRT1021"). 682 683config DCDC_VALUE 684 hex "DCDC value for VDD_SOC" 685 default 0x13 686 687config ADJUST_DCDC 688 bool "Adjust internal DCDC output" 689 690config BYPASS_LDO_LPSR 691 bool "Bypass LDO lpsr" 692 693config ADJUST_LDO 694 bool "Adjust LDO setting" 695 696config PM_MCUX_GPC 697 bool "MCUX general power controller driver" 698 699config PM_MCUX_DCDC 700 bool "MCUX dcdc converter module driver" 701 702config PM_MCUX_PMU 703 bool "MCUX power management unit driver" 704 705menuconfig NXP_IMX_RT_BOOT_HEADER 706 bool "Boot header" 707 depends on (!BOOTLOADER_MCUBOOT) && CPU_CORTEX_M7 708 help 709 Enable data structures required by the boot ROM to boot the 710 application from an external flash device. 711 712if NXP_IMX_RT_BOOT_HEADER 713 714choice BOOT_DEVICE 715 prompt "Boot device selection" 716 default BOOT_FLEXSPI_NOR 717 718config BOOT_FLEXSPI_NOR 719 bool "FlexSPI serial NOR" 720 721config BOOT_FLEXSPI_NAND 722 bool "FlexSPI serial NAND" 723 724config BOOT_SEMC_NOR 725 bool "SEMC parallel NOR" 726 727config BOOT_SEMC_NAND 728 bool "SEMC parallel NAND" 729 730endchoice 731 732config FLEXSPI_CONFIG_BLOCK_OFFSET 733 hex "FlexSPI config block offset" 734 default 0x0 if BOOT_FLEXSPI_NOR 735 help 736 FlexSPI configuration block consists of parameters regarding specific 737 flash devices including read command sequence, quad mode enablement 738 sequence (optional), etc. The boot ROM expects FlexSPI configuration 739 parameter to be presented in serial nor flash. 740 741config IMAGE_VECTOR_TABLE_OFFSET 742 hex "Image vector table offset" 743 default 0x1000 if BOOT_FLEXSPI_NOR || BOOT_SEMC_NOR 744 default 0x400 if BOOT_FLEXSPI_NAND || BOOT_SEMC_NAND 745 help 746 The Image Vector Table (IVT) provides the boot ROM with pointers to 747 the application entry point and device configuration data. The boot 748 ROM requires a fixed IVT offset for each type of boot device. 749 750config DEVICE_CONFIGURATION_DATA 751 bool "Device configuration data" 752 help 753 Device configuration data (DCD) provides a sequence of commands to 754 the boot ROM to initialize components such as an SDRAM. This is 755 useful if your application expects components like SDRAM to be 756 initialized at boot time. 757 758endif # NXP_IMX_RT_BOOT_HEADER 759 760choice CODE_LOCATION 761 prompt "Code location selection" 762 default CODE_ITCM 763 764config CODE_SEMC 765 bool "Link code into external SEMC-controlled memory" 766 imply NXP_IMX_RT_BOOT_HEADER if !BOOTLOADER_MCUBOOT 767 768config CODE_ITCM 769 bool "Link code into internal instruction tightly coupled memory (ITCM)" 770 imply NXP_IMX_RT_BOOT_HEADER if !BOOTLOADER_MCUBOOT 771 772config CODE_FLEXSPI 773 bool "Link code into external FlexSPI-controlled memory" 774 imply NXP_IMX_RT_BOOT_HEADER if !BOOTLOADER_MCUBOOT 775 776config CODE_FLEXSPI2 777 bool "Link code into internal FlexSPI-controlled memory" 778 imply NXP_IMX_RT_BOOT_HEADER if !BOOTLOADER_MCUBOOT 779 780config CODE_SRAM0 781 bool "Link code into RAM_L memory (RAM_L)" 782 imply NXP_IMX_RT_BOOT_HEADER if !BOOTLOADER_MCUBOOT 783 784config CODE_OCRAM 785 bool "Link code into OCRAM memory (OCRAM-M4)" 786 imply NXP_IMX_RT_BOOT_HEADER if !BOOTLOADER_MCUBOOT 787 788endchoice 789 790config NXP_IMX_EXTERNAL_SDRAM 791 bool "Allow access to external SDRAM region" 792 help 793 Enable access to external SDRAM region managed by the SEMC. This 794 setting should be enabled when the application uses SDRAM, or 795 an MPU region will be defined to disable cached access to the 796 SDRAM memory space. 797 798config NXP_IMX_RT_ROM_RAMLOADER 799 depends on !FLASH_MCUX_FLEXSPI_XIP && NXP_IMX_RT_BOOT_HEADER 800 # Required so that debugger will load image to correct offset 801 select BUILD_OUTPUT_HEX 802 bool "Create output image that IMX RT ROM can load from FlexSPI to ram" 803 help 804 Builds an output image that the IMX RT BootROM can load from the 805 FlexSPI boot device into RAM region. The image will be loaded 806 from FLEXSPI into the region specified by `zephyr,flash` node. 807 808# Setup LMA adjustment if using the RAMLOADER feature of ROM 809FLASH_CHOSEN := zephyr,flash 810FLASH_BASE := $(dt_chosen_reg_addr_hex,$(FLASH_CHOSEN)) 811FLEXSPI_BASE := $(dt_node_reg_addr_hex,/soc/spi@402a8000,1) 812config BUILD_OUTPUT_ADJUST_LMA 813 default "$(FLEXSPI_BASE) - $(FLASH_BASE)" if NXP_IMX_RT_ROM_RAMLOADER 814 815config SECOND_CORE_MCUX 816 bool "Dual core operation on the RT11xx series" 817 depends on SOC_SERIES_IMX_RT11XX 818 help 819 Indicates the second core will be enabled, and the part will run 820 in dual core mode. Enables dual core operation on the RT11xx series, 821 by booting an image targeting the Cortex-M4 from the Cortex-M7 CPU. 822 The M4 image will be loaded from flash into RAM based off a 823 generated header specifying the VMA and LMA of each memory section 824 to load 825 826config IMXRT1XXX_CODE_CACHE 827 bool "Code cache" 828 default y 829 help 830 Enable Code cache at boot for IMXRT1xxx series 831 832config IMXRT1XXX_DATA_CACHE 833 bool "Data cache" 834 default y 835 help 836 Enable Data cache at boot for IMXRT1xxx series 837 838endif # SOC_SERIES_IMX_RT 839
