1 /*
2 * Copyright (c) 2023 Nuvoton Technology Corporation.
3 *
4 * SPDX-License-Identifier: Apache-2.0
5 */
6
7 #include <zephyr/devicetree.h>
8 #include <zephyr/drivers/clock_control/clock_control_numaker.h>
9 /* Hardware and starter kit includes. */
10 #include <NuMicro.h>
11
z_arm_platform_init(void)12 void z_arm_platform_init(void)
13 {
14 SystemInit();
15
16 /* Unlock protected registers */
17 SYS_UnlockReg();
18
19 /*
20 * -------------------
21 * Init System Clock
22 * -------------------
23 */
24
25 #if DT_NODE_HAS_PROP(DT_NODELABEL(scc), hxt)
26 /* Enable/disable 4~24 MHz external crystal oscillator (HXT) */
27 if (DT_ENUM_IDX(DT_NODELABEL(scc), hxt) == NUMAKER_SCC_CLKSW_ENABLE) {
28 CLK_EnableXtalRC(CLK_PWRCTL_HXTEN_Msk);
29 /* Wait for HXT clock ready */
30 CLK_WaitClockReady(CLK_STATUS_HXTSTB_Msk);
31 } else if (DT_ENUM_IDX(DT_NODELABEL(scc), hxt) == NUMAKER_SCC_CLKSW_DISABLE) {
32 CLK_DisableXtalRC(CLK_PWRCTL_HXTEN_Msk);
33 }
34 #endif
35
36 #if DT_NODE_HAS_PROP(DT_NODELABEL(scc), lxt)
37 /* Enable/disable 32.768 kHz low-speed external crystal oscillator (LXT) */
38 if (DT_ENUM_IDX(DT_NODELABEL(scc), lxt) == NUMAKER_SCC_CLKSW_ENABLE) {
39 CLK_EnableXtalRC(CLK_PWRCTL_LXTEN_Msk);
40 /* Wait for LXT clock ready */
41 CLK_WaitClockReady(CLK_STATUS_LXTSTB_Msk);
42 } else if (DT_ENUM_IDX(DT_NODELABEL(scc), lxt) == NUMAKER_SCC_CLKSW_DISABLE) {
43 CLK_DisableXtalRC(CLK_PWRCTL_LXTEN_Msk);
44 }
45 #endif
46
47 /* Enable 12 MHz high-speed internal RC oscillator (HIRC) */
48 CLK_EnableXtalRC(CLK_PWRCTL_HIRCEN_Msk);
49 /* Wait for HIRC clock ready */
50 CLK_WaitClockReady(CLK_STATUS_HIRCSTB_Msk);
51
52 /* Enable 10 KHz low-speed internal RC oscillator (LIRC) */
53 CLK_EnableXtalRC(CLK_PWRCTL_LIRCEN_Msk);
54 /* Wait for LIRC clock ready */
55 CLK_WaitClockReady(CLK_STATUS_LIRCSTB_Msk);
56
57 #if DT_NODE_HAS_PROP(DT_NODELABEL(scc), hirc48)
58 /* Enable/disable 48 MHz high-speed internal RC oscillator (HIRC48) */
59 if (DT_ENUM_IDX(DT_NODELABEL(scc), hirc48) == NUMAKER_SCC_CLKSW_ENABLE) {
60 CLK_EnableXtalRC(CLK_PWRCTL_HIRC48EN_Msk);
61 /* Wait for HIRC48 clock ready */
62 CLK_WaitClockReady(CLK_STATUS_HIRC48STB_Msk);
63 } else if (DT_ENUM_IDX(DT_NODELABEL(scc), hirc48) == NUMAKER_SCC_CLKSW_DISABLE) {
64 CLK_DisableXtalRC(CLK_PWRCTL_HIRC48EN_Msk);
65 }
66 #endif
67
68 #if DT_NODE_HAS_PROP(DT_NODELABEL(scc), clk_pclkdiv)
69 /* Set CLK_PCLKDIV register on request */
70 CLK->PCLKDIV = DT_PROP(DT_NODELABEL(scc), clk_pclkdiv);
71 #endif
72
73 #if DT_NODE_HAS_PROP(DT_NODELABEL(scc), core_clock)
74 /* Set core clock (HCLK) on request */
75 CLK_SetCoreClock(DT_PROP(DT_NODELABEL(scc), core_clock));
76 #endif
77
78 /*
79 * Update System Core Clock
80 * User can use SystemCoreClockUpdate() to calculate SystemCoreClock.
81 */
82 SystemCoreClockUpdate();
83
84 /* Lock protected registers */
85 SYS_LockReg();
86 }
87
