1# Nuvoton Cortex-M4 Embedded Controller
2
3# Copyright (c) 2020 Nuvoton Technology Corporation.
4# SPDX-License-Identifier: Apache-2.0
5
6config SOC_FAMILY_NPCX
7	bool
8
9if SOC_FAMILY_NPCX
10config SOC_FAMILY
11	string
12	default "nuvoton_npcx"
13
14menuconfig NPCX_HEADER
15	bool "The output binary with NPCX binary header"
16	help
17	  On NPCX series chip, the NPCX ROM code loads firmware image from flash
18	  to RAM by the firmware binary header setting. Enable this to invoke
19	  the 'ecst' which generates the NPCX firmware header.
20
21if NPCX_HEADER
22
23config NPCX_IMAGE_OUTPUT_BIN
24	bool "Build npcx binary in BIN format"
25	default y
26	help
27	  Build a "raw" binary zephyr/zephyr.npcx.bin in the build directory.
28	  The name of this file can be customized with CONFIG_KERNEL_BIN_NAME.
29
30config NPCX_IMAGE_OUTPUT_HEX
31	bool "Build npcx binary in HEX format"
32	depends on NPCX_IMAGE_OUTPUT_BIN
33	help
34	  Build an HEX binary zephyr/zephyr.npcx.hex in the build directory.
35	  This is generated from the npcx BIN image.
36	  The name of this file can be customized with CONFIG_KERNEL_BIN_NAME.
37
38config NPCX_HEADER_CHIP
39	string
40	default "npcx7m6" if SOC_NPCX7M6FB || SOC_NPCX7M6FC
41	default "npcx7m7" if SOC_NPCX7M7FC
42	default "npcx9m3" if SOC_NPCX9M3F
43	default "npcx9m6" if SOC_NPCX9M6F
44	default "npcx9m7" if SOC_NPCX9M7F
45	default "npcx4m3" if SOC_NPCX4M3F
46	default "npcx4m8" if SOC_NPCX4M8F
47
48choice NPCX_HEADER_SPI_MAX_CLOCK_CHOICE
49	prompt "Clock rate to use for SPI flash"
50	default NPCX_HEADER_SPI_MAX_CLOCK_20
51	help
52	  This selects the max clock rate that will be used for loading firmware
53	  binary from flash to RAM.
54
55config NPCX_HEADER_SPI_MAX_CLOCK_20
56	bool "SPI flash max clock rate of 20 MHz"
57
58config NPCX_HEADER_SPI_MAX_CLOCK_25
59	bool "SPI flash max clock rate of 25 MHz"
60
61config NPCX_HEADER_SPI_MAX_CLOCK_33
62	bool "SPI flash max clock rate of 33 MHz"
63	depends on !SOC_SERIES_NPCX9
64
65config NPCX_HEADER_SPI_MAX_CLOCK_40
66	bool "SPI flash max clock rate of 40 MHz"
67
68config NPCX_HEADER_SPI_MAX_CLOCK_50
69	bool "SPI flash max clock rate of 50 MHz"
70endchoice
71
72config NPCX_HEADER_SPI_MAX_CLOCK
73	int
74	default 20 if NPCX_HEADER_SPI_MAX_CLOCK_20
75	default 25 if NPCX_HEADER_SPI_MAX_CLOCK_25
76	default 33 if NPCX_HEADER_SPI_MAX_CLOCK_33
77	default 40 if NPCX_HEADER_SPI_MAX_CLOCK_40
78	default 50 if NPCX_HEADER_SPI_MAX_CLOCK_50
79
80choice NPCX_HEADER_SPI_READ_MODE_CHOICE
81	prompt "Reading mode used by the SPI flash"
82	default NPCX_HEADER_SPI_READ_MODE_NORMAL
83	help
84	  This sets the reading mode that can be used by the SPI flash.
85	  Reading modes supported are normal, fast, dual, and quad.
86
87config NPCX_HEADER_SPI_READ_MODE_NORMAL
88	bool "SPI flash operates with normal reading mode"
89
90config NPCX_HEADER_SPI_READ_MODE_FAST
91	bool "SPI flash operates with fast reading mode"
92
93config NPCX_HEADER_SPI_READ_MODE_DUAL
94	bool "SPI flash operates with dual reading mode"
95
96config NPCX_HEADER_SPI_READ_MODE_QUAD
97	bool "SPI flash operates with quad reading mode"
98endchoice
99
100config NPCX_HEADER_SPI_READ_MODE
101	string
102	default "normal" if NPCX_HEADER_SPI_READ_MODE_NORMAL
103	default "fast" if NPCX_HEADER_SPI_READ_MODE_FAST
104	default "dual" if NPCX_HEADER_SPI_READ_MODE_DUAL
105	default "quad" if NPCX_HEADER_SPI_READ_MODE_QUAD
106
107choice NPCX_HEADER_CORE_CLOCK_SPI_CLOCK_RATIO_CHOICE
108	prompt "Core clock to SPI flash clock ratio"
109	default NPCX_HEADER_CORE_CLOCK_SPI_CLOCK_RATIO_1
110	help
111	  This sets the clock ratio (core clock / SPI clock)
112
113config NPCX_HEADER_CORE_CLOCK_SPI_CLOCK_RATIO_1
114	bool "NPCX SPI clock ratio 1"
115	help
116	  The SPI flash clock has the same frequency as the core clock.
117
118config NPCX_HEADER_CORE_CLOCK_SPI_CLOCK_RATIO_2
119	bool "NPCX SPI clock ratio 2"
120	help
121	  The core clock frequency is twice the flash clock frequency.
122endchoice
123
124config NPCX_HEADER_CORE_CLOCK_SPI_CLOCK_RATIO
125	int
126	default 1 if NPCX_HEADER_CORE_CLOCK_SPI_CLOCK_RATIO_1
127	default 2 if NPCX_HEADER_CORE_CLOCK_SPI_CLOCK_RATIO_2
128
129config NPCX_HEADER_ENABLE_HEADER_CRC
130	bool "Header crc check"
131	help
132	  When enabled, the header will be verified at boot using a crc
133	  checksum.
134
135config NPCX_HEADER_ENABLE_FIRMWARE_CRC
136	bool "Firmware image crc check"
137	help
138	  When enabled, the firmware image will be verified at boot using a
139	  crc checksum.
140
141choice NPCX_HEADER_FLASH_SIZE_CHOICE
142	prompt "Flash size"
143	default NPCX_HEADER_FLASH_SIZE_0P5M_1M if SOC_SERIES_NPCX7 || \
144						  SOC_SERIES_NPCX9
145	default NPCX_HEADER_FLASH_SIZE_16M
146	help
147	  This sets the SPI flash size.
148
149config NPCX_HEADER_FLASH_SIZE_0P5M_1M
150	bool "SPI flash size 0.5M or 1M Bytes"
151	help
152	  The SPI flash size is 0.5M or 1M Bytes.
153
154config NPCX_HEADER_FLASH_SIZE_2M
155	bool "SPI flash size 2M Bytes"
156	help
157	  The SPI flash size is 2M Bytes.
158
159config NPCX_HEADER_FLASH_SIZE_4M
160	bool "SPI flash size 4M Bytes"
161	help
162	  The SPI flash size is 4M Bytes.
163
164config NPCX_HEADER_FLASH_SIZE_8M
165	bool "SPI flash size 8M Bytes"
166	help
167	  The SPI flash size is 8M Bytes.
168
169config NPCX_HEADER_FLASH_SIZE_16M
170	bool "SPI flash size 16M Bytes"
171	help
172	  The SPI flash size is 16M Bytes.
173endchoice
174
175config NPCX_HEADER_FLASH_SIZE
176	int
177	default 1 if NPCX_HEADER_FLASH_SIZE_0P5M_1M
178	default 2 if NPCX_HEADER_FLASH_SIZE_2M
179	default 4 if NPCX_HEADER_FLASH_SIZE_4M
180	default 8 if NPCX_HEADER_FLASH_SIZE_8M
181	default 16 if NPCX_HEADER_FLASH_SIZE_16M
182
183endif # NPCX_HEADER
184
185# Select SoC Part No. and configuration options
186source "soc/arm/nuvoton_npcx/*/Kconfig.soc"
187
188config NPCX_PM_TRACE
189	bool "Trace System Power Management in NPCX family"
190	depends on PM
191	help
192	  Internal config to enable runtime power management traces.
193
194endif # SOC_FAMILY_NPCX
195