1# Nordic Semiconductor nRF52 MCU line
2
3# Copyright (c) 2016-2019 Nordic Semiconductor ASA
4# SPDX-License-Identifier: Apache-2.0
5
6if SOC_SERIES_NRF52X
7
8config SOC_NRF52805
9	bool
10
11config SOC_NRF52810
12	bool
13
14config SOC_NRF52811
15	bool
16
17config SOC_NRF52820
18	bool
19
20config SOC_NRF52832
21	bool
22	select CPU_CORTEX_M_HAS_DWT
23	select CPU_HAS_FPU
24
25config SOC_NRF52833
26	bool
27	select SOC_COMPATIBLE_NRF52833
28	select CPU_CORTEX_M_HAS_DWT
29	select CPU_HAS_FPU
30
31config SOC_NRF52840
32	bool
33	select CPU_CORTEX_M_HAS_DWT
34	select CPU_HAS_FPU
35
36choice
37	prompt "nRF52x MCU Selection"
38
39config SOC_NRF52805_CAAA
40	bool "NRF52805_CAAA"
41	select SOC_NRF52805
42
43config SOC_NRF52810_QFAA
44	bool "NRF52810_QFAA"
45	select SOC_NRF52810
46
47config SOC_NRF52811_QFAA
48	bool "NRF52811_QFAA"
49	select SOC_NRF52811
50
51config SOC_NRF52820_QDAA
52	bool "NRF52820_QDAA"
53	select SOC_NRF52820
54
55config SOC_NRF52832_CIAA
56	bool "NRF52832_CIAA"
57	select SOC_NRF52832
58
59config SOC_NRF52832_QFAA
60	bool "NRF52832_QFAA"
61	select SOC_NRF52832
62
63config SOC_NRF52832_QFAB
64	bool "NRF52832_QFAB"
65	select SOC_NRF52832
66
67config SOC_NRF52833_QDAA
68	bool "NRF52833_QDAA"
69	select SOC_NRF52833
70
71config SOC_NRF52833_QIAA
72	bool "NRF52833_QIAA"
73	select SOC_NRF52833
74
75config SOC_NRF52840_QFAA
76	bool "NRF52840_QFAA"
77	select SOC_NRF52840
78
79config SOC_NRF52840_QIAA
80	bool "NRF52840_QIAA"
81	select SOC_NRF52840
82
83endchoice
84
85config SOC_DCDC_NRF52X
86	bool
87	help
88	  Enable nRF52 series System on Chip DC/DC converter.
89
90config SOC_DCDC_NRF52X_HV
91	bool
92	depends on SOC_NRF52840_QIAA
93	help
94	  Enable nRF52 series System on Chip High Voltage DC/DC converter.
95
96config GPIO_AS_PINRESET
97	bool "[DEPRECATED] GPIO as pin reset (reset button)"
98	select DEPRECATED
99	help
100	  This option is deprecated, use devicetree instead. Example
101	  configuration:
102
103	  &uicr {
104	      gpio-as-nreset;
105	  };
106
107config NRF_ENABLE_ICACHE
108	bool "The instruction cache (I-Cache)"
109	depends on SOC_NRF52832 || SOC_NRF52833 || SOC_NRF52840
110	default y
111
112config NRF52_ANOMALY_132_DELAY_US
113	int "Anomaly 132 workaround delay (microseconds)"
114	default 330
115	range 0 330
116	depends on NRF52_ANOMALY_132_WORKAROUND
117	help
118	  Due to Anomaly 132 LF RC source may not start if restarted in certain
119	  window after stopping (230 us to 330 us). Software reset also stops the
120	  clock so if clock is initiated in certain window, the clock may also fail
121	  to start at reboot. A delay is added before starting LF clock to ensure
122	  that anomaly conditions are not met. Delay should be long enough to ensure
123	  that clock is started later than 330 us after reset. If crystal oscillator
124	  (XO) is used then low frequency clock initially starts with RC and then
125	  seamlessly switches to XO which has much longer startup time thus,
126	  depending on application, workaround may also need to be applied.
127	  Additional drivers initialization increases initialization time and delay
128	  may be shortened. Workaround is disabled by setting delay to 0.
129
130config NRF52_ANOMALY_198_WORKAROUND
131	bool "Anomaly 198 workaround"
132	default y
133	depends on SOC_NRF52840
134	depends on NRFX_SPIM3
135	help
136	  This anomaly applies to IC revisions "Engineering B" up to "3", the most
137	  recent one.
138
139config NRF52_ANOMALY_109_WORKAROUND
140	bool "Anomaly 109 workaround"
141	default y
142	depends on SOC_NRF52832
143	depends on NRFX_SPIS || NRFX_SPIM || NRFX_TWIM || NRFX_PWM
144	help
145	  Due to Anomaly 109 the first byte sent out by these peripherals is
146	  sometimes wrong. This occurs when the system enters IDLE and stops the
147	  64MHz clock at the same time as the peripheral that is using DMA is started.
148	  This anomaly applies to IC revisions up to "3", the most recent one.
149
150endif # SOC_SERIES_NRF52X
151