1 /* 2 * Copyright (c) 2021 Microchip Technology Inc. and its subsidiaries. 3 * 4 * SPDX-License-Identifier: Apache-2.0 5 */ 6 7 #ifndef _MEC172X_P80BD_H 8 #define _MEC172X_P80BD_H 9 10 #include <stdint.h> 11 #include <stddef.h> 12 13 #define MCHP_P80BD_0_BASE_ADDR 0x400f8000u 14 15 /* HDATA - Write-Only 32-bit */ 16 #define MCHP_P80BD_HDATA_OFS 0x00u 17 #define MCHP_P80BD_HDATA_MASK GENMASK(31, 0) 18 19 /* 20 * EC-only Data/Attributes 16-bit 21 * b[7:0] = data byte from capture FIFO 22 * b[15:8] = data attributes 23 */ 24 #define MCHP_P80BD_ECDA_OFS 0x100u 25 #define MCHP_P80BD_ECDA_MASK 0x7fffu 26 #define MCHP_P80BD_ECDA_DPOS 0 27 #define MCHP_P80BD_ECDA_APOS 8 28 #define MCHP_P80BD_ECDA_DMSK 0xffu 29 #define MCHP_P80BD_ECDA_AMSK 0x7f00u 30 #define MCHP_P80BD_ECDA_LANE_POS 8 31 #define MCHP_P80BD_ECDA_LANE_MSK 0x0300u 32 #define MCHP_P80BD_ECDA_LANE_0 0x0000u 33 #define MCHP_P80BD_ECDA_LANE_1 0x0100u 34 #define MCHP_P80BD_ECDA_LANE_2 0x0200u 35 #define MCHP_P80BD_ECDA_LANE_3 0x0300u 36 #define MCHP_P80BD_ECDA_LEN_POS 10 37 #define MCHP_P80BD_ECDA_LEN_MSK 0x0c00u 38 #define MCHP_P80BD_ECDA_LEN_1 0x0000u 39 #define MCHP_P80BD_ECDA_LEN_2 0x0400u 40 #define MCHP_P80BD_ECDA_LEN_4 0x0800u 41 #define MCHP_P80BD_ECDA_LEN_INVAL 0x0c00u 42 #define MCHP_P80BD_ECDA_NE BIT(12) 43 #define MCHP_P80BD_ECDA_OVR BIT(13) 44 #define MCHP_P80BD_ECDA_THR BIT(14) 45 46 /* Configuration */ 47 #define MCHP_P80BD_CFG_OFS 0x104u 48 #define MCHP_P80BD_CFG_MASK 0x80000703u 49 #define MCHP_P80BD_CFG_FLUSH_FIFO BIT(0) /* WO */ 50 #define MCHP_P80BD_CFG_SNAP_CLR BIT(1) /* WO */ 51 #define MCHP_P80BD_CFG_FIFO_THR_POS 8 52 #define MCHP_P80BD_CFG_FIFO_THR_MSK 0x700u 53 #define MCHP_P80BD_CFG_FIFO_THR_1 0x000u 54 #define MCHP_P80BD_CFG_FIFO_THR_4 0x100u 55 #define MCHP_P80BD_CFG_FIFO_THR_8 0x200u 56 #define MCHP_P80BD_CFG_FIFO_THR_16 0x300u 57 #define MCHP_P80BD_CFG_FIFO_THR_20 0x400u 58 #define MCHP_P80BD_CFG_FIFO_THR_24 0x500u 59 #define MCHP_P80BD_CFG_FIFO_THR_28 0x600u 60 #define MCHP_P80BD_CFG_FIFO_THR_30 0x700u 61 #define MCHP_P80BD_CFG_SRST BIT(31) /* WO */ 62 63 /* Status and Interrupt Enable 16-bit */ 64 #define MCHP_P80BD_SI_OFS 0x108u 65 #define MCHP_P80BD_SI_MASK 0x107u 66 #define MCHP_P80BD_SI_STS_MASK 0x007u 67 #define MCHP_P80BD_SI_IEN_MASK 0x100u 68 #define MCHP_P80BD_SI_NE_STS BIT(0) 69 #define MCHP_P80BD_SI_OVR_STS BIT(1) 70 #define MCHP_P80BD_SI_THR_STS BIT(2) 71 #define MCHP_P80BD_SI_THR_IEN BIT(8) 72 73 /* Snapshot 32-bit (RO) */ 74 #define MCHP_P80BD_SS_OFS 0x10Cu 75 #define MCHP_P80BD_SS_MASK 0xffffffffu 76 77 /* Capture 32-bit (RO). Current 4-byte Port 80 capture value */ 78 #define MCHP_P80BD_CAP_OFS 0x110u 79 80 /** @brief BIOS Debug Port 80h and Alias port capture registers. */ 81 struct p80bd_regs { 82 volatile uint32_t HDATA; 83 uint8_t RSVD1[0x100 - 0x04]; 84 volatile uint32_t EC_DA; 85 volatile uint32_t CONFIG; 86 volatile uint32_t STS_IEN; 87 volatile uint32_t SNAPSHOT; 88 volatile uint32_t CAPTURE; 89 uint8_t RSVD2[0x330 - 0x114]; 90 volatile uint32_t ACTV; 91 uint8_t RSVD3[0x400 - 0x334]; 92 volatile uint8_t ALIAS_HDATA; 93 uint8_t RSVD4[0x730 - 0x401]; 94 volatile uint32_t ALIAS_ACTV; 95 uint8_t RSVD5[0x7f0 - 0x734]; 96 volatile uint32_t ALIAS_BLS; 97 }; 98 99 #endif /* #ifndef _MEC172X_P80BD_H */ 100
