1 /*
2  * Copyright (c) 2022, Teslabs Engineering S.L.
3  * SPDX-License-Identifier: Apache-2.0
4  */
5 
6 #ifndef SOC_ARM_GIGADEVICE_GD32F3X0_GD32_REGS_H_
7 #define SOC_ARM_GIGADEVICE_GD32F3X0_GD32_REGS_H_
8 
9 #include <zephyr/sys/util_macro.h>
10 
11 /* RCU */
12 #define RCU_CFG0_OFFSET      0x04U
13 #define RCU_AHBEN_OFFSET     0x14U
14 #define RCU_APB2EN_OFFSET    0x18U
15 #define RCU_APB1EN_OFFSET    0x1CU
16 #define RCU_ADDAPB1EN_OFFSET 0xF8U
17 
18 #define RCU_CFG0_AHBPSC_POS  4U
19 #define RCU_CFG0_AHBPSC_MSK  (BIT_MASK(4) << RCU_CFG0_AHBPSC_POS)
20 #define RCU_CFG0_APB1PSC_POS 8U
21 #define RCU_CFG0_APB1PSC_MSK (BIT_MASK(3) << RCU_CFG0_APB1PSC_POS)
22 #define RCU_CFG0_APB2PSC_POS 11U
23 #define RCU_CFG0_APB2PSC_MSK (BIT_MASK(3) << RCU_CFG0_APB2PSC_POS)
24 
25 #endif /* SOC_ARM_GIGADEVICE_GD32F3X0_GD32_REGS_H_ */
26