1 /*
2 * Copyright (c) 2018, Cypress
3 *
4 * SPDX-License-Identifier: Apache-2.0
5 */
6
7 #include <zephyr/device.h>
8 #include <zephyr/init.h>
9 #include <zephyr/arch/cpu.h>
10 #include <zephyr/irq.h>
11
12 #include "cy_syslib.h"
13 #include "cy_gpio.h"
14 #include "cy_scb_uart.h"
15 #include "cy_syslib.h"
16 #include "cy_syspm.h"
17 #include "cy_sysclk.h"
18
19 #define CY_CFG_SYSCLK_CLKFAST_ENABLED 1
20 #define CY_CFG_SYSCLK_FLL_ENABLED 1
21 #define CY_CFG_SYSCLK_CLKHF0_ENABLED 1
22 #define CY_CFG_SYSCLK_CLKHF0_FREQ_MHZ 100UL
23 #define CY_CFG_SYSCLK_ILO_ENABLED 1
24 #define CY_CFG_SYSCLK_IMO_ENABLED 1
25 #define CY_CFG_SYSCLK_CLKLF_ENABLED 1
26 #define CY_CFG_SYSCLK_CLKPATH0_ENABLED 1
27 #define CY_CFG_SYSCLK_CLKPATH1_ENABLED 1
28 #define CY_CFG_SYSCLK_CLKPATH2_ENABLED 1
29 #define CY_CFG_SYSCLK_CLKPATH3_ENABLED 1
30 #define CY_CFG_SYSCLK_CLKPATH4_ENABLED 1
31 #define CY_CFG_SYSCLK_CLKPERI_ENABLED 1
32 #define CY_CFG_SYSCLK_CLKSLOW_ENABLED 1
33 #define CY_CFG_PWR_ENABLED 1
34 #define CY_CFG_PWR_USING_LDO 1
35 #define CY_CFG_PWR_USING_PMIC 0
36 #define CY_CFG_PWR_LDO_VOLTAGE CY_SYSPM_LDO_VOLTAGE_1_1V
37 #define CY_CFG_PWR_VDDA_MV 3300
38 #define CY_CFG_PWR_USING_ULP 0
39
40 /* Dummy symbols, requres for cy_sysint.c module.
41 * NOTE: in this PSoC 6 integration, PSoC 6 Zephyr drivers (uart, spi, gpio)
42 * do not use cy_sysint.c implementation to handle interrupt routine.
43 * Instead this they use IRQ_CONNECT to define ISR.
44 */
45 uint32_t __ramVectors;
46 uint32_t __Vectors;
47
48 static const cy_stc_fll_manual_config_t srss_0__clock_0__fll_0__fllConfig = {
49 .fllMult = 500u,
50 .refDiv = 20u,
51 .ccoRange = CY_SYSCLK_FLL_CCO_RANGE4,
52 .enableOutputDiv = true,
53 .lockTolerance = 10u,
54 .igain = 9u,
55 .pgain = 5u,
56 .settlingCount = 8u,
57 .outputMode = CY_SYSCLK_FLLPLL_OUTPUT_AUTO,
58 .cco_Freq = 355u,
59 };
60
Cy_SysClk_ClkFastInit(void)61 static inline void Cy_SysClk_ClkFastInit(void)
62 {
63 Cy_SysClk_ClkFastSetDivider(0u);
64 }
Cy_SysClk_FllInit(void)65 static inline void Cy_SysClk_FllInit(void)
66 {
67 Cy_SysClk_FllManualConfigure(&srss_0__clock_0__fll_0__fllConfig);
68 Cy_SysClk_FllEnable(200000u);
69 }
Cy_SysClk_ClkHf0Init(void)70 static inline void Cy_SysClk_ClkHf0Init(void)
71 {
72 Cy_SysClk_ClkHfSetSource(0u, CY_SYSCLK_CLKHF_IN_CLKPATH0);
73 Cy_SysClk_ClkHfSetDivider(0u, CY_SYSCLK_CLKHF_NO_DIVIDE);
74 Cy_SysClk_ClkHfEnable(0u);
75
76 }
Cy_SysClk_IloInit(void)77 static inline void Cy_SysClk_IloInit(void)
78 {
79 Cy_SysClk_IloEnable();
80 Cy_SysClk_IloHibernateOn(true);
81 }
Cy_SysClk_ClkLfInit(void)82 static inline void Cy_SysClk_ClkLfInit(void)
83 {
84 Cy_SysClk_ClkLfSetSource(CY_SYSCLK_CLKLF_IN_ILO);
85 }
Cy_SysClk_ClkPath0Init(void)86 static inline void Cy_SysClk_ClkPath0Init(void)
87 {
88 Cy_SysClk_ClkPathSetSource(0u, CY_SYSCLK_CLKPATH_IN_IMO);
89 }
Cy_SysClk_ClkPath1Init(void)90 static inline void Cy_SysClk_ClkPath1Init(void)
91 {
92 Cy_SysClk_ClkPathSetSource(1u, CY_SYSCLK_CLKPATH_IN_IMO);
93 }
Cy_SysClk_ClkPath2Init(void)94 static inline void Cy_SysClk_ClkPath2Init(void)
95 {
96 Cy_SysClk_ClkPathSetSource(2u, CY_SYSCLK_CLKPATH_IN_IMO);
97 }
Cy_SysClk_ClkPath3Init(void)98 static inline void Cy_SysClk_ClkPath3Init(void)
99 {
100 Cy_SysClk_ClkPathSetSource(3u, CY_SYSCLK_CLKPATH_IN_IMO);
101 }
Cy_SysClk_ClkPath4Init(void)102 static inline void Cy_SysClk_ClkPath4Init(void)
103 {
104 Cy_SysClk_ClkPathSetSource(4u, CY_SYSCLK_CLKPATH_IN_IMO);
105 }
Cy_SysClk_ClkPeriInit(void)106 static inline void Cy_SysClk_ClkPeriInit(void)
107 {
108 Cy_SysClk_ClkPeriSetDivider(1u);
109 }
Cy_SysClk_ClkSlowInit(void)110 static inline void Cy_SysClk_ClkSlowInit(void)
111 {
112 Cy_SysClk_ClkSlowSetDivider(0u);
113 }
114
115
init_cycfg_platform(void)116 static void init_cycfg_platform(void)
117 {
118 /* Set worst case memory wait states (! ultra low power, 150 MHz), will
119 * update at the end
120 */
121 Cy_SysLib_SetWaitStates(false, 150);
122 #ifdef CY_CFG_PWR_ENABLED
123 /* Configure power mode */
124 #if CY_CFG_PWR_USING_LDO
125 Cy_SysPm_LdoSetVoltage(CY_CFG_PWR_LDO_VOLTAGE);
126 #else
127 Cy_SysPm_BuckEnable(CY_CFG_PWR_SIMO_VOLTAGE);
128 #endif
129 /* Configure PMIC */
130 Cy_SysPm_UnlockPmic();
131 #if CY_CFG_PWR_USING_PMIC
132 Cy_SysPm_PmicEnableOutput();
133 #else
134 Cy_SysPm_PmicDisableOutput();
135 #endif
136 #endif
137 /* Enable all source clocks */
138 #ifdef CY_CFG_SYSCLK_PILO_ENABLED
139 Cy_SysClk_PiloInit();
140 #endif
141
142 #ifdef CY_CFG_SYSCLK_WCO_ENABLED
143 Cy_SysClk_WcoInit();
144 #endif
145
146 #ifdef CY_CFG_SYSCLK_CLKLF_ENABLED
147 Cy_SysClk_ClkLfInit();
148 #endif
149
150 #ifdef CY_CFG_SYSCLK_ALTHF_ENABLED
151 Cy_SysClk_AltHfInit();
152 #endif
153
154 #ifdef CY_CFG_SYSCLK_ECO_ENABLED
155 Cy_SysClk_EcoInit();
156 #endif
157
158 #ifdef CY_CFG_SYSCLK_EXTCLK_ENABLED
159 Cy_SysClk_ExtClkInit();
160 #endif
161
162 /* Configure CPU clock dividers */
163 #ifdef CY_CFG_SYSCLK_CLKFAST_ENABLED
164 Cy_SysClk_ClkFastInit();
165 #endif
166
167 #ifdef CY_CFG_SYSCLK_CLKPERI_ENABLED
168 Cy_SysClk_ClkPeriInit();
169 #endif
170
171 #ifdef CY_CFG_SYSCLK_CLKSLOW_ENABLED
172 Cy_SysClk_ClkSlowInit();
173 #endif
174
175 /* Configure HF clocks */
176 #ifdef CY_CFG_SYSCLK_CLKHF0_ENABLED
177 Cy_SysClk_ClkHf0Init();
178 #endif
179 #ifdef CY_CFG_SYSCLK_CLKHF1_ENABLED
180 Cy_SysClk_ClkHf1Init();
181 #endif
182 #ifdef CY_CFG_SYSCLK_CLKHF2_ENABLED
183 Cy_SysClk_ClkHf2Init();
184 #endif
185 #ifdef CY_CFG_SYSCLK_CLKHF3_ENABLED
186 Cy_SysClk_ClkHf3Init();
187 #endif
188 #ifdef CY_CFG_SYSCLK_CLKHF4_ENABLED
189 Cy_SysClk_ClkHf4Init();
190 #endif
191 #ifdef CY_CFG_SYSCLK_CLKHF5_ENABLED
192 Cy_SysClk_ClkHf5Init();
193 #endif
194 #ifdef CY_CFG_SYSCLK_CLKHF6_ENABLED
195 Cy_SysClk_ClkHf6Init();
196 #endif
197 #ifdef CY_CFG_SYSCLK_CLKHF7_ENABLED
198 Cy_SysClk_ClkHf7Init();
199 #endif
200 #ifdef CY_CFG_SYSCLK_CLKHF8_ENABLED
201 Cy_SysClk_ClkHf8Init();
202 #endif
203 #ifdef CY_CFG_SYSCLK_CLKHF9_ENABLED
204 Cy_SysClk_ClkHf9Init();
205 #endif
206 #ifdef CY_CFG_SYSCLK_CLKHF10_ENABLED
207 Cy_SysClk_ClkHf10Init();
208 #endif
209 #ifdef CY_CFG_SYSCLK_CLKHF11_ENABLED
210 Cy_SysClk_ClkHf11Init();
211 #endif
212 #ifdef CY_CFG_SYSCLK_CLKHF12_ENABLED
213 Cy_SysClk_ClkHf12Init();
214 #endif
215 #ifdef CY_CFG_SYSCLK_CLKHF13_ENABLED
216 Cy_SysClk_ClkHf13Init();
217 #endif
218 #ifdef CY_CFG_SYSCLK_CLKHF14_ENABLED
219 Cy_SysClk_ClkHf14Init();
220 #endif
221 #ifdef CY_CFG_SYSCLK_CLKHF15_ENABLED
222 Cy_SysClk_ClkHf15Init();
223 #endif
224
225 /* Configure Path Clocks */
226 #ifdef CY_CFG_SYSCLK_CLKPATH0_ENABLED
227 Cy_SysClk_ClkPath0Init();
228 #endif
229 #ifdef CY_CFG_SYSCLK_CLKPATH1_ENABLED
230 Cy_SysClk_ClkPath1Init();
231 #endif
232 #ifdef CY_CFG_SYSCLK_CLKPATH2_ENABLED
233 Cy_SysClk_ClkPath2Init();
234 #endif
235 #ifdef CY_CFG_SYSCLK_CLKPATH3_ENABLED
236 Cy_SysClk_ClkPath3Init();
237 #endif
238 #ifdef CY_CFG_SYSCLK_CLKPATH4_ENABLED
239 Cy_SysClk_ClkPath4Init();
240 #endif
241 #ifdef CY_CFG_SYSCLK_CLKPATH5_ENABLED
242 Cy_SysClk_ClkPath5Init();
243 #endif
244 #ifdef CY_CFG_SYSCLK_CLKPATH6_ENABLED
245 Cy_SysClk_ClkPath6Init();
246 #endif
247 #ifdef CY_CFG_SYSCLK_CLKPATH7_ENABLED
248 Cy_SysClk_ClkPath7Init();
249 #endif
250 #ifdef CY_CFG_SYSCLK_CLKPATH8_ENABLED
251 Cy_SysClk_ClkPath8Init();
252 #endif
253 #ifdef CY_CFG_SYSCLK_CLKPATH9_ENABLED
254 Cy_SysClk_ClkPath9Init();
255 #endif
256 #ifdef CY_CFG_SYSCLK_CLKPATH10_ENABLED
257 Cy_SysClk_ClkPath10Init();
258 #endif
259 #ifdef CY_CFG_SYSCLK_CLKPATH11_ENABLED
260 Cy_SysClk_ClkPath11Init();
261 #endif
262 #ifdef CY_CFG_SYSCLK_CLKPATH12_ENABLED
263 Cy_SysClk_ClkPath12Init();
264 #endif
265 #ifdef CY_CFG_SYSCLK_CLKPATH13_ENABLED
266 Cy_SysClk_ClkPath13Init();
267 #endif
268 #ifdef CY_CFG_SYSCLK_CLKPATH14_ENABLED
269 Cy_SysClk_ClkPath14Init();
270 #endif
271 #ifdef CY_CFG_SYSCLK_CLKPATH15_ENABLED
272 Cy_SysClk_ClkPath15Init();
273 #endif
274
275 /* Configure and enable FLL */
276 #ifdef CY_CFG_SYSCLK_FLL_ENABLED
277 Cy_SysClk_FllInit();
278 #endif
279
280 /* Configure and enable PLLs */
281 #ifdef CY_CFG_SYSCLK_PLL0_ENABLED
282 Cy_SysClk_Pll0Init();
283 #endif
284 #ifdef CY_CFG_SYSCLK_PLL1_ENABLED
285 Cy_SysClk_Pll1Init();
286 #endif
287 #ifdef CY_CFG_SYSCLK_PLL2_ENABLED
288 Cy_SysClk_Pll2Init();
289 #endif
290 #ifdef CY_CFG_SYSCLK_PLL3_ENABLED
291 Cy_SysClk_Pll3Init();
292 #endif
293 #ifdef CY_CFG_SYSCLK_PLL4_ENABLED
294 Cy_SysClk_Pll4Init();
295 #endif
296 #ifdef CY_CFG_SYSCLK_PLL5_ENABLED
297 Cy_SysClk_Pll5Init();
298 #endif
299 #ifdef CY_CFG_SYSCLK_PLL6_ENABLED
300 Cy_SysClk_Pll6Init();
301 #endif
302 #ifdef CY_CFG_SYSCLK_PLL7_ENABLED
303 Cy_SysClk_Pll7Init();
304 #endif
305 #ifdef CY_CFG_SYSCLK_PLL8_ENABLED
306 Cy_SysClk_Pll8Init();
307 #endif
308 #ifdef CY_CFG_SYSCLK_PLL9_ENABLED
309 Cy_SysClk_Pll9Init();
310 #endif
311 #ifdef CY_CFG_SYSCLK_PLL10_ENABLED
312 Cy_SysClk_Pll10Init();
313 #endif
314 #ifdef CY_CFG_SYSCLK_PLL11_ENABLED
315 Cy_SysClk_Pll11Init();
316 #endif
317 #ifdef CY_CFG_SYSCLK_PLL12_ENABLED
318 Cy_SysClk_Pll12Init();
319 #endif
320 #ifdef CY_CFG_SYSCLK_PLL13_ENABLED
321 Cy_SysClk_Pll13Init();
322 #endif
323 #ifdef CY_CFG_SYSCLK_PLL14_ENABLED
324 Cy_SysClk_Pll14Init();
325 #endif
326
327 /* Configure miscellaneous clocks */
328 #ifdef CY_CFG_SYSCLK_CLKTIMER_ENABLED
329 Cy_SysClk_ClkTimerInit();
330 #endif
331
332 #ifdef CY_CFG_SYSCLK_CLKALTSYSTICK_ENABLED
333 Cy_SysClk_ClkAltSysTickInit();
334 #endif
335
336 #ifdef CY_CFG_SYSCLK_CLKPUMP_ENABLED
337 Cy_SysClk_ClkPumpInit();
338 #endif
339
340 #ifdef CY_CFG_SYSCLK_CLKBAK_ENABLED
341 Cy_SysClk_ClkBakInit();
342 #endif
343
344 /* Configure default enabled clocks */
345 #ifdef CY_CFG_SYSCLK_ILO_ENABLED
346 Cy_SysClk_IloInit();
347 #else
348 Cy_SysClk_IloDisable();
349 #endif
350
351 #ifndef CY_CFG_SYSCLK_IMO_ENABLED
352 #error the IMO must be enabled for proper chip operation
353 #endif
354
355 /* Set accurate flash wait states */
356 #if (defined(CY_CFG_PWR_ENABLED) && defined(CY_CFG_SYSCLK_CLKHF0_ENABLED))
357 Cy_SysLib_SetWaitStates(CY_CFG_PWR_USING_ULP != 0,
358 CY_CFG_SYSCLK_CLKHF0_FREQ_MHZ);
359 #endif
360 }
361
362 /**
363 * Function Name: Cy_SystemInit
364 *
365 * \brief This function is called by the start-up code for the selected device.
366 * It performs all of the necessary device configuration based on the design
367 * settings. This includes settings for the platform resources and peripheral
368 * clock.
369 *
370 */
Cy_SystemInit(void)371 void Cy_SystemInit(void)
372 {
373 /* Configure platform resources */
374 init_cycfg_platform();
375
376 /* Configure peripheral clocks */
377 Cy_SysClk_PeriphSetDivider(CY_SYSCLK_DIV_8_BIT, 0u, 0u);
378 Cy_SysClk_PeriphEnableDivider(CY_SYSCLK_DIV_8_BIT, 0u);
379
380 #if defined(CONFIG_SOC_PSOC6_M0_ENABLES_M4)
381 Cy_SysEnableCM4(DT_REG_ADDR(DT_NODELABEL(flash1)));
382 #endif
383 }
384
init_cycfg_platform_wraper(void)385 static int init_cycfg_platform_wraper(void)
386 {
387 SystemInit();
388 return 0;
389 }
390
391 SYS_INIT(init_cycfg_platform_wraper, PRE_KERNEL_1, 0);
392
