1 /* 2 * Copyright (c) 2016-2017 Piotr Mienkowski 3 * Copyright (c) 2021 ATL Electronics 4 * SPDX-License-Identifier: Apache-2.0 5 */ 6 7 /** @file 8 * @brief Cypress PSoC-6 MCU family General Purpose Input Output (GPIO) 9 * module HAL driver. 10 */ 11 12 #ifndef _CYPRESS_PSOC6_SOC_GPIO_H_ 13 #define _CYPRESS_PSOC6_SOC_GPIO_H_ 14 15 #include <zephyr/types.h> 16 #include <soc.h> 17 18 /* 19 * Pin flags/attributes 20 */ 21 22 #define SOC_GPIO_DEFAULT (0) 23 24 #define SOC_GPIO_FLAGS_POS (0) 25 #define SOC_GPIO_FLAGS_MASK (0x3F << SOC_GPIO_FLAGS_POS) 26 #define SOC_GPIO_PULLUP_POS (0) 27 #define SOC_GPIO_PULLUP (1 << SOC_GPIO_PULLUP_POS) 28 #define SOC_GPIO_PULLDOWN_POS (1) 29 #define SOC_GPIO_PULLDOWN (1 << SOC_GPIO_PULLDOWN_POS) 30 #define SOC_GPIO_OPENDRAIN_POS (2) 31 #define SOC_GPIO_OPENDRAIN (1 << SOC_GPIO_OPENDRAIN_POS) 32 #define SOC_GPIO_OPENSOURCE_POS (3) 33 #define SOC_GPIO_OPENSOURCE (1 << SOC_GPIO_OPENSOURCE_POS) 34 /* Push-Pull means Strong, see dts/pinctrl/pincfg-node.yaml */ 35 #define SOC_GPIO_PUSHPULL_POS (4) 36 #define SOC_GPIO_PUSHPULL (1 << SOC_GPIO_PUSHPULL_POS) 37 /* Input-Enable means Input-Buffer, see dts/pinctrl/pincfg-node.yaml */ 38 #define SOC_GPIO_INPUTENABLE_POS (5) 39 #define SOC_GPIO_INPUTENABLE (1 << SOC_GPIO_INPUTENABLE_POS) 40 41 /* Bit field: SOC_GPIO_IN_FILTER */ 42 #define SOC_GPIO_IN_FILTER_POS (6) 43 #define SOC_GPIO_IN_FILTER_MASK (3 << SOC_GPIO_IN_FILTER_POS) 44 #define SOC_GPIO_IN_FILTER_NONE (0 << SOC_GPIO_IN_FILTER_POS) 45 #define SOC_GPIO_IN_FILTER_DEBOUNCE (1 << SOC_GPIO_IN_FILTER_POS) 46 #define SOC_GPIO_IN_FILTER_DEGLITCH (2 << SOC_GPIO_IN_FILTER_POS) 47 48 #define SOC_GPIO_INT_ENABLE (1 << 8) 49 50 /* Bit field: SOC_GPIO_INT_TRIG */ 51 #define SOC_GPIO_INT_TRIG_POS (9) 52 #define SOC_GPIO_INT_TRIG_MASK (3 << SOC_GPIO_INT_TRIG_POS) 53 /** Interrupt is triggered by a level detection event. */ 54 #define SOC_GPIO_INT_TRIG_LEVEL (0 << SOC_GPIO_INT_TRIG_POS) 55 /** Interrupt is triggered by an edge detection event. */ 56 #define SOC_GPIO_INT_TRIG_EDGE (1 << SOC_GPIO_INT_TRIG_POS) 57 /** Interrupt is triggered by any edge detection event. */ 58 #define SOC_GPIO_INT_TRIG_DOUBLE_EDGE (2 << SOC_GPIO_INT_TRIG_POS) 59 60 /** Interrupt is triggered by a high level / rising edge detection event */ 61 #define SOC_GPIO_INT_ACTIVE_HIGH (1 << 11) 62 63 /* Bit field: SOC_GPIO_FUNC */ 64 #define SOC_GPIO_FUNC_POS (16) 65 #define SOC_GPIO_FUNC_MASK (0x1F << SOC_GPIO_FUNC_POS) 66 67 struct soc_gpio_pin { 68 GPIO_PRT_Type *regs; /** pointer to registers of the GPIO controller */ 69 uint32_t pinum; /** pin number */ 70 uint32_t flags; /** pin flags/attributes */ 71 }; 72 73 /** 74 * @brief Configure GPIO pin(s). 75 * 76 * Configure one or several pins belonging to the same GPIO port. 77 * Example scenarios: 78 * - configure pin(s) as input with debounce filter enabled. 79 * - connect pin(s) to a HSIOM function and enable pull-up. 80 * - configure pin(s) as open drain output. 81 * All pins are configured in the same way. 82 * 83 * @param pin pin's configuration data such as pin mask, pin attributes, etc. 84 */ 85 void soc_gpio_configure(const struct soc_gpio_pin *pin); 86 87 /** 88 * @brief Configure a list of GPIO pin(s). 89 * 90 * Configure an arbitrary amount of pins in an arbitrary way. Each 91 * configuration entry is a single item in an array passed as an 92 * argument to the function. 93 * 94 * @param pins an array where each item contains pin's configuration data. 95 * @param size size of the pin list. 96 */ 97 void soc_gpio_list_configure(const struct soc_gpio_pin pins[], size_t size); 98 99 #endif /* _CYPRESS_PSOC6_SOC_GPIO_H_ */ 100
