1 /* 2 * Copyright 2022 NXP 3 * 4 * SPDX-License-Identifier: Apache-2.0 5 */ 6 7 #ifndef ZEPHYR_INCLUDE_DT_BINDINGS_PINCTRL_NXP_S32_PINCTRL_H_ 8 #define ZEPHYR_INCLUDE_DT_BINDINGS_PINCTRL_NXP_S32_PINCTRL_H_ 9 10 #include <zephyr/dt-bindings/dt-util.h> 11 12 /* 13 * The NXP S32 pinmux configuration is encoded in a 32-bit field value as follows: 14 * 15 * - 0..2: Output mux Source Signal Selection (MSCR.SSS) 16 * - 3..6: Input mux Source Signal Selection (IMCR.SSS) 17 * - 7..15: Input Multiplexed Signal Configuration Register (IMCR) index 18 * - 16..24: Multiplexed Signal Configuration Register (MSCR) index 19 * - 25..27: SIUL2 instance index (0..7) 20 * - 28..31: Reserved for future use 21 */ 22 #define NXP_S32_MSCR_SSS_SHIFT 0U 23 #define NXP_S32_MSCR_SSS_MASK BIT_MASK(3) 24 #define NXP_S32_IMCR_SSS_SHIFT 3U 25 #define NXP_S32_IMCR_SSS_MASK BIT_MASK(4) 26 #define NXP_S32_IMCR_IDX_SHIFT 7U 27 #define NXP_S32_IMCR_IDX_MASK BIT_MASK(9) 28 #define NXP_S32_MSCR_IDX_SHIFT 16U 29 #define NXP_S32_MSCR_IDX_MASK BIT_MASK(9) 30 #define NXP_S32_SIUL2_IDX_SHIFT 25U 31 #define NXP_S32_SIUL2_IDX_MASK BIT_MASK(3) 32 33 #define NXP_S32_PINMUX_MSCR_SSS(cfg) \ 34 (((cfg) & NXP_S32_MSCR_SSS_MASK) << NXP_S32_MSCR_SSS_SHIFT) 35 36 #define NXP_S32_PINMUX_IMCR_SSS(cfg) \ 37 (((cfg) & NXP_S32_IMCR_SSS_MASK) << NXP_S32_IMCR_SSS_SHIFT) 38 39 #define NXP_S32_PINMUX_IMCR_IDX(cfg) \ 40 (((cfg) & NXP_S32_IMCR_IDX_MASK) << NXP_S32_IMCR_IDX_SHIFT) 41 42 #define NXP_S32_PINMUX_MSCR_IDX(cfg) \ 43 (((cfg) & NXP_S32_MSCR_IDX_MASK) << NXP_S32_MSCR_IDX_SHIFT) 44 45 #define NXP_S32_PINMUX_SIUL2_IDX(cfg) \ 46 (((cfg) & NXP_S32_SIUL2_IDX_MASK) << NXP_S32_SIUL2_IDX_SHIFT) 47 48 #define NXP_S32_PINMUX_GET_MSCR_SSS(cfg) \ 49 (((cfg) >> NXP_S32_MSCR_SSS_SHIFT) & NXP_S32_MSCR_SSS_MASK) 50 51 #define NXP_S32_PINMUX_GET_IMCR_SSS(cfg) \ 52 (((cfg) >> NXP_S32_IMCR_SSS_SHIFT) & NXP_S32_IMCR_SSS_MASK) 53 54 #define NXP_S32_PINMUX_GET_IMCR_IDX(cfg) \ 55 (((cfg) >> NXP_S32_IMCR_IDX_SHIFT) & NXP_S32_IMCR_IDX_MASK) 56 57 #define NXP_S32_PINMUX_GET_MSCR_IDX(cfg) \ 58 (((cfg) >> NXP_S32_MSCR_IDX_SHIFT) & NXP_S32_MSCR_IDX_MASK) 59 60 #define NXP_S32_PINMUX_GET_SIUL2_IDX(cfg) \ 61 (((cfg) >> NXP_S32_SIUL2_IDX_SHIFT) & NXP_S32_SIUL2_IDX_MASK) 62 63 /** 64 * @brief Utility macro to build NXP S32 pinmux property for pinctrl nodes. 65 * 66 * @param siul2_idx SIUL2 instance index 67 * @param mscr_idx Multiplexed Signal Configuration Register (MSCR) index 68 * @param mscr_sss Output mux Source Signal Selection (MSCR.SSS) 69 * @param imcr_idx Input Multiplexed Signal Configuration Register (IMCR) index 70 * @param imcr_sss Input mux Source Signal Selection (IMCR.SSS) 71 */ 72 #define NXP_S32_PINMUX(siul2_idx, mscr_idx, mscr_sss, imcr_idx, imcr_sss) \ 73 (NXP_S32_PINMUX_SIUL2_IDX(siul2_idx) | NXP_S32_PINMUX_MSCR_IDX(mscr_idx) \ 74 | NXP_S32_PINMUX_MSCR_SSS(mscr_sss) | NXP_S32_PINMUX_IMCR_IDX(imcr_idx) \ 75 | NXP_S32_PINMUX_IMCR_SSS(imcr_sss)) 76 77 #endif /* ZEPHYR_INCLUDE_DT_BINDINGS_PINCTRL_NXP_NXP_S32_PINCTRL_H_ */ 78
