1 /*
2  * Copyright (c) 2016 Cadence Design Systems, Inc.
3  * Copyright (c) 2019 Stephanos Ioannidis <root@stephanos.io>
4  *
5  * SPDX-License-Identifier: Apache-2.0
6  */
7 
8 #ifndef ZEPHYR_INCLUDE_ARCH_XTENSA_ARCH_INLINES_H_
9 #define ZEPHYR_INCLUDE_ARCH_XTENSA_ARCH_INLINES_H_
10 
11 #ifndef _ASMLANGUAGE
12 
13 #include <zephyr/kernel_structs.h>
14 #include <zsr.h>
15 
16 #define XTENSA_RSR(sr) \
17 	({uint32_t v; \
18 	 __asm__ volatile ("rsr." sr " %0" : "=a"(v)); \
19 	 v; })
20 
21 #define XTENSA_WSR(sr, v) \
22 	do { \
23 		__asm__ volatile ("wsr." sr " %0" : : "r"(v)); \
24 	} while (false)
25 
26 #define XTENSA_RUR(ur) \
27 	({uint32_t v; \
28 	 __asm__ volatile ("rur." ur " %0" : "=a"(v)); \
29 	 v; })
30 
31 #define XTENSA_WUR(ur, v) \
32 	do { \
33 		__asm__ volatile ("wur." ur " %0" : : "r"(v)); \
34 	} while (false)
35 
arch_curr_cpu(void)36 static ALWAYS_INLINE _cpu_t *arch_curr_cpu(void)
37 {
38 	_cpu_t *cpu;
39 
40 	cpu = (_cpu_t *)XTENSA_RSR(ZSR_CPU_STR);
41 
42 	return cpu;
43 }
44 
arch_proc_id(void)45 static ALWAYS_INLINE uint32_t arch_proc_id(void)
46 {
47 	uint32_t prid;
48 
49 	__asm__ volatile("rsr %0, PRID" : "=r"(prid));
50 	return prid;
51 }
52 
53 #ifdef CONFIG_SOC_HAS_RUNTIME_NUM_CPUS
54 extern unsigned int soc_num_cpus;
55 #endif
56 
arch_num_cpus(void)57 static ALWAYS_INLINE unsigned int arch_num_cpus(void)
58 {
59 #ifdef CONFIG_SOC_HAS_RUNTIME_NUM_CPUS
60 	return soc_num_cpus;
61 #else
62 	return CONFIG_MP_MAX_NUM_CPUS;
63 #endif
64 }
65 
66 #endif /* !_ASMLANGUAGE */
67 
68 #endif /* ZEPHYR_INCLUDE_ARCH_XTENSA_ARCH_INLINES_H_ */
69