1 /* 2 * Copyright (c) 2015, Wind River Systems, Inc. 3 * 4 * SPDX-License-Identifier: Apache-2.0 5 */ 6 7 #ifndef _CORTEX_M_CPU_H 8 #define _CORTEX_M_CPU_H 9 10 #ifdef _ASMLANGUAGE 11 12 #define _SCS_BASE_ADDR _PPB_INT_SCS 13 14 /* ICSR defines */ 15 #define _SCS_ICSR (_SCS_BASE_ADDR + 0xd04) 16 #define _SCS_ICSR_PENDSV (1 << 28) 17 #define _SCS_ICSR_UNPENDSV (1 << 27) 18 #define _SCS_ICSR_RETTOBASE (1 << 11) 19 20 #define _SCS_MPU_CTRL (_SCS_BASE_ADDR + 0xd94) 21 22 /* CONTROL defines */ 23 #define _CONTROL_FPCA_Msk (1 << 2) 24 25 /* EXC_RETURN defines */ 26 #define _EXC_RETURN_SPSEL_Msk (1 << 2) 27 #define _EXC_RETURN_FTYPE_Msk (1 << 4) 28 29 #else 30 #include <stdint.h> 31 32 #ifdef __cplusplus 33 extern "C" { 34 #endif 35 36 /* CP10 Access Bits */ 37 #define CPACR_CP10_Pos 20U 38 #define CPACR_CP10_Msk (3UL << CPACR_CP10_Pos) 39 #define CPACR_CP10_NO_ACCESS (0UL << CPACR_CP10_Pos) 40 #define CPACR_CP10_PRIV_ACCESS (1UL << CPACR_CP10_Pos) 41 #define CPACR_CP10_RESERVED (2UL << CPACR_CP10_Pos) 42 #define CPACR_CP10_FULL_ACCESS (3UL << CPACR_CP10_Pos) 43 44 /* CP11 Access Bits */ 45 #define CPACR_CP11_Pos 22U 46 #define CPACR_CP11_Msk (3UL << CPACR_CP11_Pos) 47 #define CPACR_CP11_NO_ACCESS (0UL << CPACR_CP11_Pos) 48 #define CPACR_CP11_PRIV_ACCESS (1UL << CPACR_CP11_Pos) 49 #define CPACR_CP11_RESERVED (2UL << CPACR_CP11_Pos) 50 #define CPACR_CP11_FULL_ACCESS (3UL << CPACR_CP11_Pos) 51 52 #ifdef CONFIG_PM_S2RAM 53 54 struct __cpu_context { 55 /* GPRs are saved onto the stack */ 56 uint32_t msp; 57 uint32_t msplim; 58 uint32_t psp; 59 uint32_t psplim; 60 uint32_t apsr; 61 uint32_t ipsr; 62 uint32_t epsr; 63 uint32_t primask; 64 uint32_t faultmask; 65 uint32_t basepri; 66 uint32_t control; 67 }; 68 69 typedef struct __cpu_context _cpu_context_t; 70 71 #endif /* CONFIG_PM_S2RAM */ 72 73 #ifdef __cplusplus 74 } 75 #endif 76 77 #endif /* _ASMLANGUAGE */ 78 79 #endif /* _CORTEX_M_CPU_H */ 80
