1/*
2 * Copyright (c) 2021 NXP
3 *
4 * SPDX-License-Identifier: Apache-2.0
5 */
6
7#include <zephyr/dt-bindings/clock/imx_ccm.h>
8#include <xtensa/xtensa.dtsi>
9#include <mem.h>
10
11/ {
12	cpus {
13		#address-cells = <1>;
14		#size-cells = <0>;
15
16		cpu0: cpu@0 {
17			device_type = "cpu";
18			compatible = "cdns,tensilica-xtensa-lx6";
19			reg = <0>;
20		};
21	};
22
23	sram0: memory@92400000 {
24		device_type = "memory";
25		compatible = "mmio-sram";
26		reg = <0x92400000 DT_SIZE_K(512)>;
27	};
28
29	sram1: memory@92c00000 {
30		device_type = "memory";
31		compatible = "mmio-sram";
32		reg = <0x92c00000 DT_SIZE_K(512)>;
33	};
34
35	soc {
36		interrupt-parent = <&irqsteer>;
37
38		irqsteer: interrupt-controller {
39			compatible = "nxp,irqsteer-intc";
40			interrupt-controller;
41			#interrupt-cells = <2>;
42		};
43
44		ccm: ccm@30380000 {
45			compatible = "nxp,imx-ccm";
46			reg = <0x30380000 DT_SIZE_K(64)>;
47			#clock-cells = <3>;
48		};
49
50		iomuxc: iomuxc@30330000 {
51			compatible = "nxp,imx-iomuxc";
52			reg = <0x30330000 DT_SIZE_K(64)>;
53			status = "okay";
54			pinctrl: pinctrl {
55				status = "okay";
56				compatible = "nxp,imx8mp-pinctrl";
57			};
58		};
59
60		/*
61		 * For now only UART4 is supported and
62		 * tested with the serial driver
63		 */
64		uart4: uart@30a60000 {
65			compatible = "nxp,imx-iuart";
66			reg = <0x30a60000 0x10000>;
67			clocks = <&ccm IMX_CCM_UART4_CLK 0x6c 24>;
68			status = "disabled";
69		};
70
71		mailbox0: mailbox@30e70000 {
72			compatible = "nxp,imx-mu-rev2";
73			reg = <0x30e70000 0x10000>;
74			interrupts = <7 0>;
75			rdc = <0>;
76			status = "disabled";
77		};
78	};
79};
80