1/*
2 * Copyright (c) 2019,2022 Intel Corporation
3 *
4 * SPDX-License-Identifier: Apache-2.0
5 */
6
7#include <xtensa/intel/intel_adsp_cavs.dtsi>
8#include <mem.h>
9
10/ {
11	cpus {
12		#address-cells = <1>;
13		#size-cells = <0>;
14
15		cpu0: cpu@0 {
16			device_type = "cpu";
17			compatible = "cdns,tensilica-xtensa-lx6";
18			reg = <0>;
19			cpu-power-states = <&d3>;
20			i-cache-line-size = <64>;
21			d-cache-line-size = <64>;
22		};
23
24		cpu1: cpu@1 {
25			device_type = "cpu";
26			compatible = "cdns,tensilica-xtensa-lx6";
27			reg = <1>;
28			cpu-power-states = <&d3>;
29		};
30
31		power-states {
32			/* PM_STATE_SOFT_OFF can be entered only by calling
33			 * pm_state_force. The procedure is triggered by IPC
34			 * from the HOST (SET_DX).
35			 */
36			d3: off {
37				compatible = "zephyr,power-state";
38				power-state-name = "soft-off";
39				min-residency-us = <2147483647>;
40				exit-latency-us = <0>;
41			};
42		};
43	};
44
45	sram0: memory@be000000 {
46		device_type = "memory";
47		compatible = "mmio-sram";
48		reg = <0xbe000000 DT_SIZE_K(1920)>;
49	};
50
51	sram1: memory@be800000 {
52		device_type = "memory";
53		compatible = "mmio-sram";
54		reg = <0xbe800000 DT_SIZE_K(64)>;
55	};
56
57	sysclk: system-clock {
58		compatible = "fixed-clock";
59		clock-frequency = <38400000>;
60		#clock-cells = <0>;
61	};
62
63	audioclk: audio-clock {
64		compatible = "fixed-clock";
65		clock-frequency = <24576000>;
66		#clock-cells = <0>;
67	};
68
69	pllclk: pll-clock {
70		compatible = "fixed-clock";
71		clock-frequency = <96000000>;
72		#clock-cells = <0>;
73	};
74
75	clkctl: clkctl {
76		compatible = "intel,adsp-shim-clkctl";
77		adsp-clkctl-clk-wovcro = <0>;
78		adsp-clkctl-clk-lpro = <1>;
79		adsp-clkctl-clk-hpro = <2>;
80		adsp-clkctl-freq-enc = <0x1a 0x20000002 0x80000002>;
81		adsp-clkctl-freq-mask = <0x10 0x20000000 0x80000000>;
82		adsp-clkctl-freq-default = <2>;
83		adsp-clkctl-freq-lowest = <0>;
84		wovcro-supported;
85	};
86
87	IMR1: memory@0xb0000000 {
88		compatible = "intel,adsp-imr";
89		reg = <0xB0000000 DT_SIZE_M(16)>;
90		block-size = <0x1000>;
91		zephyr,memory-region = "IMR1";
92	};
93
94	soc {
95		shim: shim@71f00 {
96			compatible = "intel,adsp-shim";
97			reg = <0x71f00 0x100>;
98		};
99
100		mem_window0: mem_window@71a00 {
101			compatible = "intel,adsp-mem-window";
102			reg = <0x71a00 0x8>;
103			offset = <0x4000>;
104			memory = <&sram0>;
105			initialize;
106			read-only;
107		};
108		mem_window1: mem_window@71a08 {
109			compatible = "intel,adsp-mem-window";
110			reg = <0x71a08 0x8>;
111			memory = <&sram0>;
112		};
113
114		mem_window2: mem_window@71a10 {
115			compatible = "intel,adsp-mem-window";
116			reg = <0x71a10 0x8>;
117			memory = <&sram0>;
118		};
119
120		mem_window3: mem_window@71a18 {
121			compatible = "intel,adsp-mem-window";
122			reg = <0x71a18 0x8>;
123			memory = <&sram0>;
124			read-only;
125		};
126
127		timer: timer {
128			compatible = "intel,adsp-timer";
129			syscon = <&shim>;
130		};
131
132		sspbase: ssp_base@71c00 {
133			compatible = "intel,cavs-sspbase";
134			reg = <0x71c00 0x100>;
135		};
136
137		l2lm: l2lm@71d00 {
138			compatible = "intel,cavs-l2lm";
139			reg = <0x71d00 0x20>;
140		};
141
142		adsp_host_ipc: cavs_host_ipc@71e00 {
143			compatible = "intel,adsp-host-ipc";
144			reg = <0x71e00 0x30>;
145			interrupts = <7 0 0>;
146			interrupt-parent = <&cavs_intc0>;
147		};
148
149		core_intc: core_intc@0 {
150			compatible = "cdns,xtensa-core-intc";
151			reg = <0x00 0x400>;
152			interrupt-controller;
153			#interrupt-cells = <3>;
154		};
155
156		cavs_intc0: cavs@78800  {
157			compatible = "intel,cavs-intc";
158			reg = <0x78800 0x10>;
159			interrupt-controller;
160			#interrupt-cells = <3>;
161			interrupts = <6 0 0>;
162			interrupt-parent = <&core_intc>;
163		};
164
165		cavs_intc1: cavs@78810  {
166			compatible = "intel,cavs-intc";
167			reg = <0x78810 0x10>;
168			interrupt-controller;
169			#interrupt-cells = <3>;
170			interrupts = <0xA 0 0>;
171			interrupt-parent = <&core_intc>;
172		};
173
174		cavs_intc2: cavs@78820  {
175			compatible = "intel,cavs-intc";
176			reg = <0x78820 0x10>;
177			interrupt-controller;
178			#interrupt-cells = <3>;
179			interrupts = <0XD 0 0>;
180			interrupt-parent = <&core_intc>;
181		};
182
183		cavs_intc3: cavs@78830  {
184			compatible = "intel,cavs-intc";
185			reg = <0x78830 0x10>;
186			interrupt-controller;
187			#interrupt-cells = <3>;
188			interrupts = <0x10 0 0>;
189			interrupt-parent = <&core_intc>;
190		};
191
192		adsp_idc: idc@1200 {
193			compatible = "intel,adsp-idc";
194			reg = <0x1200 0x80>;
195			interrupts = <8 0 0>;
196			interrupt-parent = <&cavs_intc0>;
197		};
198
199		tlb: tlb@3000 {
200			compatible = "intel,adsp-tlb";
201			reg = <0x3000 0x1000>;
202			paddr-size = <11>;
203		};
204
205		dmic0: dmic0@10000 {
206			compatible = "intel,dai-dmic";
207			reg = <0x10000 0x8000>;
208			shim = <0x71E80>;
209			fifo = <0x0008>;
210			interrupts = <0x08 0 0>;
211			interrupt-parent = <&cavs_intc3>;
212		};
213
214		dmic1: dmic1@10000 {
215			compatible = "intel,dai-dmic";
216			reg = <0x10000 0x8000>;
217			shim = <0x71E80>;
218			fifo = <0x0108>;
219			interrupts = <0x09 0 0>;
220			interrupt-parent = <&cavs_intc3>;
221		};
222
223		/*
224		 * FIXME this is modeling individual alh channels/instances
225		 * with node labels, which has problems. A better representation
226		 * is discussed here:
227		 *
228		 * https://github.com/zephyrproject-rtos/zephyr/pull/50287#discussion_r974591009
229		 */
230		alh0: alh0@71000 {
231			compatible = "intel,alh-dai";
232			reg = <0x00071000 0x00071200>;
233
234			status = "okay";
235		};
236
237		alh1: alh1@71000 {
238			compatible = "intel,alh-dai";
239			reg = <0x00071000 0x00071200>;
240
241			status = "okay";
242		};
243
244		ssp0: ssp@77000 {
245			compatible = "intel,ssp-dai";
246			#address-cells = <1>;
247			#size-cells = <0>;
248			reg = <0x00077000 0x200
249			       0x00078C00 0x008>;
250			interrupts = <0x01 0 0>;
251			interrupt-parent = <&cavs_intc3>;
252			dmas = <&lpgpdma0 2
253				&lpgpdma0 3>;
254			dma-names = "tx", "rx";
255
256			status = "okay";
257		};
258
259		ssp1: ssp@77200 {
260			compatible = "intel,ssp-dai";
261			#address-cells = <1>;
262			#size-cells = <0>;
263			reg = <0x00077200 0x200
264			       0x00078C00 0x008>;
265			interrupts = <0x01 0 0>;
266			interrupt-parent = <&cavs_intc3>;
267			dmas = <&lpgpdma0 4
268				&lpgpdma0 5>;
269			dma-names = "tx", "rx";
270
271			status = "okay";
272		};
273
274		ssp2: ssp@77400 {
275			compatible = "intel,ssp-dai";
276			#address-cells = <1>;
277			#size-cells = <0>;
278			reg = <0x00077400 0x200
279			       0x00078C00 0x008>;
280			interrupts = <0x02 0 0>;
281			interrupt-parent = <&cavs_intc3>;
282			dmas = <&lpgpdma0 6
283				&lpgpdma0 7>;
284			dma-names = "tx", "rx";
285
286			status = "okay";
287		};
288
289		ssp3: ssp@77600 {
290			compatible = "intel,ssp-dai";
291			#address-cells = <1>;
292			#size-cells = <0>;
293			reg = <0x00077600 0x200
294			       0x00078C00 0x008>;
295			interrupts = <0x03 0 0>;
296			interrupt-parent = <&cavs_intc3>;
297			dmas = <&lpgpdma0 8
298				&lpgpdma0 9>;
299			dma-names = "tx", "rx";
300
301			status = "okay";
302		};
303
304		ssp4: ssp@77800 {
305			compatible = "intel,ssp-dai";
306			#address-cells = <1>;
307			#size-cells = <0>;
308			reg = <0x00077800 0x200
309			       0x00078C00 0x008>;
310			interrupts = <0x03 0 0>;
311			interrupt-parent = <&cavs_intc3>;
312			dmas = <&lpgpdma0 10
313				&lpgpdma0 11>;
314			dma-names = "tx", "rx";
315
316			status = "okay";
317		};
318
319		ssp5: ssp@77a00 {
320			compatible = "intel,ssp-dai";
321			#address-cells = <1>;
322			#size-cells = <0>;
323			reg = <0x00077A00 0x200
324			       0x00078C00 0x008>;
325			interrupts = <0x03 0 0>;
326			interrupt-parent = <&cavs_intc3>;
327			dmas = <&lpgpdma0 12
328				&lpgpdma0 13>;
329			dma-names = "tx", "rx";
330
331			status = "okay";
332		};
333	};
334
335	hdas {
336		#address-cells = <1>;
337		#size-cells = <0>;
338
339		hda0: hda@0 {
340			compatible = "intel,hda-dai";
341			status = "okay";
342			reg = <0>;
343		};
344		hda1: hda@1 {
345			compatible = "intel,hda-dai";
346			status = "okay";
347			reg = <1>;
348		};
349		hda2: hda@2 {
350			compatible = "intel,hda-dai";
351			status = "okay";
352			reg = <2>;
353		};
354		hda3: hda@3 {
355			compatible = "intel,hda-dai";
356			status = "okay";
357			reg = <3>;
358		};
359		hda4: hda@4 {
360			compatible = "intel,hda-dai";
361			status = "okay";
362			reg = <4>;
363		};
364		hda5: hda@5 {
365			compatible = "intel,hda-dai";
366			status = "okay";
367			reg = <5>;
368		};
369		hda6: hda@6 {
370			compatible = "intel,hda-dai";
371			status = "okay";
372			reg = <6>;
373		};
374		hda7: hda@7 {
375			compatible = "intel,hda-dai";
376			status = "okay";
377			reg = <7>;
378		};
379		hda8: hda@8 {
380			compatible = "intel,hda-dai";
381			status = "okay";
382			reg = <8>;
383		};
384		hda9: hda@9 {
385			compatible = "intel,hda-dai";
386			status = "okay";
387			reg = <9>;
388		};
389		hda10: hda@a {
390			compatible = "intel,hda-dai";
391			status = "okay";
392			reg = <0x0a>;
393		};
394		hda11: hda@b {
395			compatible = "intel,hda-dai";
396			status = "okay";
397			reg = <0x0b>;
398		};
399		hda12: hda@c {
400			compatible = "intel,hda-dai";
401			status = "okay";
402			reg = <0x0c>;
403		};
404		hda13: hda@d {
405			compatible = "intel,hda-dai";
406			status = "okay";
407			reg = <0x0d>;
408		};
409		hda14: hda@e {
410			compatible = "intel,hda-dai";
411			status = "okay";
412			reg = <0x0e>;
413		};
414		hda15: hda@f {
415			compatible = "intel,hda-dai";
416			status = "okay";
417			reg = <0x0f>;
418		};
419	};
420};
421