1/*
2 * Copyright (c) 2019 Intel Corporation
3 *
4 * SPDX-License-Identifier: Apache-2.0
5 */
6
7#include <xtensa/intel/intel_adsp_cavs.dtsi>
8#include <mem.h>
9
10/ {
11	cpus {
12		#address-cells = <1>;
13		#size-cells = <0>;
14
15		cpu0: cpu@0 {
16			device_type = "cpu";
17			compatible = "cdns,tensilica-xtensa-lx6";
18			reg = <0>;
19			i-cache-line-size = <64>;
20			d-cache-line-size = <64>;
21		};
22
23		cpu1: cpu@1 {
24			device_type = "cpu";
25			compatible = "cdns,tensilica-xtensa-lx6";
26			reg = <1>;
27		};
28
29	};
30
31	sram0: memory@be000000 {
32		device_type = "memory";
33		compatible = "mmio-sram";
34		reg = <0xbe000000 DT_SIZE_K(1024)>;
35	};
36
37	sram1: memory@be800000 {
38		device_type = "memory";
39		compatible = "mmio-sram";
40		reg = <0xbe800000 DT_SIZE_K(64)>;
41	};
42
43	soc {
44		shim: shim@71f00 {
45			compatible = "intel,adsp-shim";
46			reg = <0x71f00 0x100>;
47		};
48
49		timer: timer {
50			compatible = "intel,adsp-timer";
51			syscon = <&shim>;
52		};
53
54		mem_window0: mem_window@71a00 {
55			compatible = "intel,adsp-mem-window";
56			reg = <0x71a00 0x8>;
57			offset = <0x4000>;
58			memory = <&sram0>;
59			initialize;
60			read-only;
61		};
62		mem_window1: mem_window@71a08 {
63			compatible = "intel,adsp-mem-window";
64			reg = <0x71a08 0x8>;
65			memory = <&sram0>;
66		};
67
68		mem_window2: mem_window@71a10 {
69			compatible = "intel,adsp-mem-window";
70			reg = <0x71a10 0x8>;
71			memory = <&sram0>;
72		};
73
74		mem_window3: mem_window@71a18 {
75			compatible = "intel,adsp-mem-window";
76			reg = <0x71a18 0x8>;
77			memory = <&sram0>;
78			read-only;
79		};
80
81		l2lm: l2lm@71d00 {
82			compatible = "intel,cavs-l2lm";
83			reg = <0x71d00 0x20>;
84		};
85
86		core_intc: core_intc@0 {
87			compatible = "cdns,xtensa-core-intc";
88			reg = <0x00 0x400>;
89			interrupt-controller;
90			#interrupt-cells = <3>;
91		};
92
93		adsp_host_ipc: cavs_host_ipc@71e00 {
94			compatible = "intel,adsp-host-ipc";
95			reg = <0x71e00 0x30>;
96			interrupts = <7 0 0>;
97			interrupt-parent = <&cavs_intc0>;
98		};
99
100		cavs_intc0: cavs@78800  {
101			compatible = "intel,cavs-intc";
102			reg = <0x78800 0x10>;
103			interrupt-controller;
104			#interrupt-cells = <3>;
105			interrupts = <6 0 0>;
106			interrupt-parent = <&core_intc>;
107		};
108
109		cavs_intc1: cavs@78810  {
110			compatible = "intel,cavs-intc";
111			reg = <0x78810 0x10>;
112			interrupt-controller;
113			#interrupt-cells = <3>;
114			interrupts = <0xA 0 0>;
115			interrupt-parent = <&core_intc>;
116		};
117
118		cavs_intc2: cavs@78820  {
119			compatible = "intel,cavs-intc";
120			reg = <0x78820 0x10>;
121			interrupt-controller;
122			#interrupt-cells = <3>;
123			interrupts = <0XD 0 0>;
124			interrupt-parent = <&core_intc>;
125		};
126
127		cavs_intc3: cavs@78830  {
128			compatible = "intel,cavs-intc";
129			reg = <0x78830 0x10>;
130			interrupt-controller;
131			#interrupt-cells = <3>;
132			interrupts = <0x10 0 0>;
133			interrupt-parent = <&core_intc>;
134		};
135
136		adsp_idc: idc@1200 {
137			compatible = "intel,adsp-idc";
138			reg = <0x1200 0x80>;
139			interrupts = <8 0 0>;
140			interrupt-parent = <&cavs_intc0>;
141		};
142
143	};
144};
145