1/* 2 * Copyright (c) 2017-2019 Intel Corporation. 3 * 4 * SPDX-License-Identifier: Apache-2.0 5 */ 6 7#include "skeleton.dtsi" 8#include <zephyr/dt-bindings/interrupt-controller/intel-ioapic.h> 9#include <zephyr/dt-bindings/i2c/i2c.h> 10#include <zephyr/dt-bindings/pcie/pcie.h> 11 12/ { 13 cpus { 14 #address-cells = <1>; 15 #size-cells = <0>; 16 17 cpu@0 { 18 device_type = "cpu"; 19 compatible = "intel,apollo-lake"; 20 d-cache-line-size = <64>; 21 reg = <0>; 22 }; 23 24 }; 25 26 dram0: memory@0 { 27 device_type = "memory"; 28 reg = <0x0 DT_DRAM_SIZE>; 29 }; 30 31 intc: ioapic@fec00000 { 32 compatible = "intel,ioapic"; 33 #address-cells = <1>; 34 #interrupt-cells = <3>; 35 reg = <0xfec00000 0x1000>; 36 interrupt-controller; 37 }; 38 39 intc_loapic: loapic@fee00000 { 40 compatible = "intel,loapic"; 41 reg = <0xfee00000 0x1000>; 42 interrupt-controller; 43 #interrupt-cells = <3>; 44 #address-cells = <1>; 45 }; 46 47 pcie0: pcie0 { 48 #address-cells = <1>; 49 #size-cells = <1>; 50 compatible = "intel,pcie"; 51 ranges; 52 53 uart0: uart0 { 54 compatible = "ns16550"; 55 56 vendor-id = <0x8086>; 57 device-id = <0x5abc>; 58 59 reg-shift = <2>; 60 clock-frequency = <1843200>; 61 interrupts = <PCIE_IRQ_DETECT IRQ_TYPE_LOWEST_LEVEL_LOW 3>; 62 interrupt-parent = <&intc>; 63 status = "okay"; 64 current-speed = <115200>; 65 }; 66 67 uart1: uart1 { 68 compatible = "ns16550"; 69 70 vendor-id = <0x8086>; 71 device-id = <0x5abe>; 72 73 reg-shift = <2>; 74 clock-frequency = <1843200>; 75 interrupts = <PCIE_IRQ_DETECT IRQ_TYPE_LOWEST_LEVEL_LOW 3>; 76 interrupt-parent = <&intc>; 77 78 status = "okay"; 79 current-speed = <115200>; 80 }; 81 82 uart2: uart2 { 83 compatible = "ns16550"; 84 85 vendor-id = <0x8086>; 86 device-id = <0x5ac0>; 87 88 reg-shift = <2>; 89 clock-frequency = <1843200>; 90 interrupts = <PCIE_IRQ_DETECT IRQ_TYPE_LOWEST_LEVEL_LOW 3>; 91 interrupt-parent = <&intc>; 92 93 status = "okay"; 94 current-speed = <115200>; 95 }; 96 97 uart3: uart3 { 98 compatible = "ns16550"; 99 100 vendor-id = <0x8086>; 101 device-id = <0x5aee>; 102 103 reg-shift = <2>; 104 clock-frequency = <1843200>; 105 interrupts = <PCIE_IRQ_DETECT IRQ_TYPE_LOWEST_LEVEL_LOW 3>; 106 interrupt-parent = <&intc>; 107 108 status = "okay"; 109 current-speed = <115200>; 110 }; 111 112 i2c0: i2c0 { 113 compatible = "snps,designware-i2c"; 114 clock-frequency = <I2C_BITRATE_STANDARD>; 115 #address-cells = <1>; 116 #size-cells = <0>; 117 vendor-id = <0x8086>; 118 device-id = <0x5aac>; 119 interrupts = <PCIE_IRQ_DETECT IRQ_TYPE_LOWEST_LEVEL_LOW 3>; 120 interrupt-parent = <&intc>; 121 122 status = "okay"; 123 }; 124 125 i2c1: i2c1 { 126 compatible = "snps,designware-i2c"; 127 clock-frequency = <I2C_BITRATE_STANDARD>; 128 #address-cells = <1>; 129 #size-cells = <0>; 130 vendor-id = <0x8086>; 131 device-id = <0x5aae>; 132 interrupts = <PCIE_IRQ_DETECT IRQ_TYPE_LOWEST_LEVEL_LOW 3>; 133 interrupt-parent = <&intc>; 134 135 status = "okay"; 136 }; 137 138 i2c2: i2c2 { 139 compatible = "snps,designware-i2c"; 140 clock-frequency = <I2C_BITRATE_STANDARD>; 141 #address-cells = <1>; 142 #size-cells = <0>; 143 vendor-id = <0x8086>; 144 device-id = <0x5ab0>; 145 interrupts = <PCIE_IRQ_DETECT IRQ_TYPE_LOWEST_LEVEL_LOW 3>; 146 interrupt-parent = <&intc>; 147 148 status = "okay"; 149 }; 150 151 i2c3: i2c3 { 152 compatible = "snps,designware-i2c"; 153 clock-frequency = <I2C_BITRATE_STANDARD>; 154 #address-cells = <1>; 155 #size-cells = <0>; 156 vendor-id = <0x8006>; 157 device-id = <0x5ab2>; 158 interrupts = <PCIE_IRQ_DETECT IRQ_TYPE_LOWEST_LEVEL_LOW 3>; 159 interrupt-parent = <&intc>; 160 161 status = "okay"; 162 }; 163 164 i2c4: i2c4 { 165 compatible = "snps,designware-i2c"; 166 clock-frequency = <I2C_BITRATE_STANDARD>; 167 #address-cells = <1>; 168 #size-cells = <0>; 169 vendor-id = <0x8086>; 170 device-id = <0x5ab4>; 171 interrupts = <PCIE_IRQ_DETECT IRQ_TYPE_LOWEST_LEVEL_LOW 3>; 172 interrupt-parent = <&intc>; 173 174 status = "okay"; 175 }; 176 177 i2c5: i2c5{ 178 compatible = "snps,designware-i2c"; 179 clock-frequency = <I2C_BITRATE_STANDARD>; 180 #address-cells = <1>; 181 #size-cells = <0>; 182 vendor-id = <0x8086>; 183 device-id = <0x5ab6>; 184 interrupts = <PCIE_IRQ_DETECT IRQ_TYPE_LOWEST_LEVEL_LOW 3>; 185 interrupt-parent = <&intc>; 186 187 status = "okay"; 188 }; 189 190 i2c6: i2c6 { 191 compatible = "snps,designware-i2c"; 192 clock-frequency = <I2C_BITRATE_STANDARD>; 193 #address-cells = <1>; 194 #size-cells = <0>; 195 vendor-id = <0x8086>; 196 device-id = <0x5ab8>; 197 interrupts = <PCIE_IRQ_DETECT IRQ_TYPE_LOWEST_LEVEL_LOW 3>; 198 interrupt-parent = <&intc>; 199 200 status = "okay"; 201 }; 202 203 i2c7: i2c7 { 204 compatible = "snps,designware-i2c"; 205 clock-frequency = <I2C_BITRATE_STANDARD>; 206 #address-cells = <1>; 207 #size-cells = <0>; 208 vendor-id = <0x8086>; 209 device-id = <0x5aba>; 210 interrupts = <PCIE_IRQ_DETECT IRQ_TYPE_LOWEST_LEVEL_LOW 3>; 211 interrupt-parent = <&intc>; 212 213 status = "okay"; 214 }; 215 }; 216 217 soc { 218 #address-cells = <1>; 219 #size-cells = <1>; 220 compatible = "simple-bus"; 221 ranges; 222 223 vtd: vtd@fed65000 { 224 compatible = "intel,vt-d"; 225 226 reg = <0xfed65000 0x1000>; 227 228 status = "okay"; 229 }; 230 231 gpio_n_000_031: gpio@d0c50000 { 232 compatible = "intel,gpio"; 233 reg = <0xd0c50000 0x1000>; 234 interrupts = <14 IRQ_TYPE_LOWEST_LEVEL_LOW 3>; 235 interrupt-parent = <&intc>; 236 237 gpio-controller; 238 #gpio-cells = <2>; 239 240 ngpios = <32>; 241 pin-offset = <0>; 242 243 status = "okay"; 244 }; 245 246 gpio_n_032_063: gpio@d0c50001 { 247 compatible = "intel,gpio"; 248 reg = <0xd0c50001 0x1000>; 249 interrupts = <14 IRQ_TYPE_LOWEST_LEVEL_LOW 3>; 250 interrupt-parent = <&intc>; 251 252 gpio-controller; 253 #gpio-cells = <2>; 254 255 ngpios = <32>; 256 pin-offset = <32>; 257 258 status = "okay"; 259 }; 260 261 gpio_n_064_077: gpio@d0c50002 { 262 compatible = "intel,gpio"; 263 reg = <0xd0c50002 0x1000>; 264 interrupts = <14 IRQ_TYPE_LOWEST_LEVEL_LOW 3>; 265 interrupt-parent = <&intc>; 266 267 gpio-controller; 268 #gpio-cells = <2>; 269 270 ngpios = <14>; 271 pin-offset = <64>; 272 273 status = "okay"; 274 }; 275 276 gpio_nw_000_031: gpio@d0c40000 { 277 compatible = "intel,gpio"; 278 reg = <0xd0c40000 0x1000>; 279 interrupts = <14 IRQ_TYPE_LOWEST_LEVEL_LOW 3>; 280 interrupt-parent = <&intc>; 281 282 gpio-controller; 283 #gpio-cells = <2>; 284 285 ngpios = <32>; 286 pin-offset = <0>; 287 288 status = "okay"; 289 }; 290 291 gpio_nw_032_063: gpio@d0c40001 { 292 compatible = "intel,gpio"; 293 reg = <0xd0c40001 0x1000>; 294 interrupts = <14 IRQ_TYPE_LOWEST_LEVEL_LOW 3>; 295 interrupt-parent = <&intc>; 296 297 gpio-controller; 298 #gpio-cells = <2>; 299 300 ngpios = <32>; 301 pin-offset = <32>; 302 303 status = "okay"; 304 }; 305 306 gpio_nw_064_076: gpio@d0c40002 { 307 compatible = "intel,gpio"; 308 reg = <0xd0c40002 0x1000>; 309 interrupts = <14 IRQ_TYPE_LOWEST_LEVEL_LOW 3>; 310 interrupt-parent = <&intc>; 311 312 gpio-controller; 313 #gpio-cells = <2>; 314 315 ngpios = <13>; 316 pin-offset = <64>; 317 318 status = "okay"; 319 }; 320 321 gpio_w_000_031: gpio@d0c70000 { 322 compatible = "intel,gpio"; 323 reg = <0xd0c70000 0x1000>; 324 interrupts = <14 IRQ_TYPE_LOWEST_LEVEL_LOW 3>; 325 interrupt-parent = <&intc>; 326 327 gpio-controller; 328 #gpio-cells = <2>; 329 330 ngpios = <32>; 331 pin-offset = <0>; 332 333 status = "okay"; 334 }; 335 336 gpio_w_032_046: gpio@d0c70001 { 337 compatible = "intel,gpio"; 338 reg = <0xd0c70001 0x1000>; 339 interrupts = <14 IRQ_TYPE_LOWEST_LEVEL_LOW 3>; 340 interrupt-parent = <&intc>; 341 342 gpio-controller; 343 #gpio-cells = <2>; 344 345 ngpios = <15>; 346 pin-offset = <32>; 347 348 status = "okay"; 349 }; 350 351 gpio_sw_000_031: gpio@d0c00000 { 352 compatible = "intel,gpio"; 353 reg = <0xd0c00000 0x1000>; 354 interrupts = <14 IRQ_TYPE_LOWEST_LEVEL_LOW 3>; 355 interrupt-parent = <&intc>; 356 357 gpio-controller; 358 #gpio-cells = <2>; 359 360 ngpios = <32>; 361 pin-offset = <0>; 362 363 status = "okay"; 364 }; 365 366 367 gpio_sw_032_042: gpio@d0c00001 { 368 compatible = "intel,gpio"; 369 reg = <0xd0c00001 0x1000>; 370 interrupts = <14 IRQ_TYPE_LOWEST_LEVEL_LOW 3>; 371 interrupt-parent = <&intc>; 372 373 gpio-controller; 374 #gpio-cells = <2>; 375 376 ngpios = <11>; 377 pin-offset = <32>; 378 379 status = "okay"; 380 }; 381 382 hpet: hpet@fed00000 { 383 compatible = "intel,hpet"; 384 reg = <0xfed00000 0x400>; 385 interrupts = <2 IRQ_TYPE_FIXED_EDGE_RISING 4>; 386 interrupt-parent = <&intc>; 387 388 status = "okay"; 389 }; 390 391 rtc: counter: rtc@70 { 392 compatible = "motorola,mc146818"; 393 reg = <0x70 0x0D 0x71 0x0D>; 394 interrupts = <8 IRQ_TYPE_LOWEST_EDGE_RISING 3>; 395 interrupt-parent = <&intc>; 396 alarms-count = <1>; 397 398 status = "okay"; 399 }; 400 }; 401 402 gpio_n: gpio-north { 403 /* n north 78 */ 404 compatible = "intel,apollo-lake-gpio"; 405 #gpio-cells = <2>; 406 gpio-map-mask = <0xffffffff 0xffffffc0>; 407 gpio-map-pass-thru = <0 0x3f>; 408 gpio-map = 409 <0 0 &gpio_n_000_031 0 0>, 410 <1 0 &gpio_n_000_031 1 0>, 411 <2 0 &gpio_n_000_031 2 0>, 412 <3 0 &gpio_n_000_031 3 0>, 413 <4 0 &gpio_n_000_031 4 0>, 414 <5 0 &gpio_n_000_031 5 0>, 415 <6 0 &gpio_n_000_031 6 0>, 416 <7 0 &gpio_n_000_031 7 0>, 417 <8 0 &gpio_n_000_031 8 0>, 418 <9 0 &gpio_n_000_031 9 0>, 419 <10 0 &gpio_n_000_031 10 0>, 420 <11 0 &gpio_n_000_031 11 0>, 421 <12 0 &gpio_n_000_031 12 0>, 422 <13 0 &gpio_n_000_031 13 0>, 423 <14 0 &gpio_n_000_031 14 0>, 424 <15 0 &gpio_n_000_031 15 0>, 425 <16 0 &gpio_n_000_031 16 0>, 426 <17 0 &gpio_n_000_031 17 0>, 427 <18 0 &gpio_n_000_031 18 0>, 428 <19 0 &gpio_n_000_031 19 0>, 429 <20 0 &gpio_n_000_031 20 0>, 430 <21 0 &gpio_n_000_031 21 0>, 431 <22 0 &gpio_n_000_031 22 0>, 432 <23 0 &gpio_n_000_031 23 0>, 433 <24 0 &gpio_n_000_031 24 0>, 434 <25 0 &gpio_n_000_031 25 0>, 435 <26 0 &gpio_n_000_031 26 0>, 436 <27 0 &gpio_n_000_031 27 0>, 437 <28 0 &gpio_n_000_031 28 0>, 438 <29 0 &gpio_n_000_031 29 0>, 439 <30 0 &gpio_n_000_031 30 0>, 440 <31 0 &gpio_n_000_031 31 0>, 441 <32 0 &gpio_n_032_063 0 0>, 442 <33 0 &gpio_n_032_063 1 0>, 443 <34 0 &gpio_n_032_063 2 0>, 444 <35 0 &gpio_n_032_063 3 0>, 445 <36 0 &gpio_n_032_063 4 0>, 446 <37 0 &gpio_n_032_063 5 0>, 447 <38 0 &gpio_n_032_063 6 0>, 448 <39 0 &gpio_n_032_063 7 0>, 449 <40 0 &gpio_n_032_063 8 0>, 450 <41 0 &gpio_n_032_063 9 0>, 451 <42 0 &gpio_n_032_063 10 0>, 452 <43 0 &gpio_n_032_063 11 0>, 453 <44 0 &gpio_n_032_063 12 0>, 454 <45 0 &gpio_n_032_063 13 0>, 455 <46 0 &gpio_n_032_063 14 0>, 456 <47 0 &gpio_n_032_063 15 0>, 457 <48 0 &gpio_n_032_063 16 0>, 458 <49 0 &gpio_n_032_063 17 0>, 459 <50 0 &gpio_n_032_063 18 0>, 460 <51 0 &gpio_n_032_063 19 0>, 461 <52 0 &gpio_n_032_063 20 0>, 462 <53 0 &gpio_n_032_063 21 0>, 463 <54 0 &gpio_n_032_063 22 0>, 464 <55 0 &gpio_n_032_063 23 0>, 465 <56 0 &gpio_n_032_063 24 0>, 466 <57 0 &gpio_n_032_063 25 0>, 467 <58 0 &gpio_n_032_063 26 0>, 468 <59 0 &gpio_n_032_063 27 0>, 469 <60 0 &gpio_n_032_063 28 0>, 470 <61 0 &gpio_n_032_063 29 0>, 471 <62 0 &gpio_n_032_063 30 0>, 472 <63 0 &gpio_n_032_063 31 0>, 473 <64 0 &gpio_n_064_077 0 0>, 474 <65 0 &gpio_n_064_077 1 0>, 475 <66 0 &gpio_n_064_077 2 0>, 476 <67 0 &gpio_n_064_077 3 0>, 477 <68 0 &gpio_n_064_077 4 0>, 478 <69 0 &gpio_n_064_077 5 0>, 479 <70 0 &gpio_n_064_077 6 0>, 480 <71 0 &gpio_n_064_077 7 0>, 481 <72 0 &gpio_n_064_077 8 0>, 482 <73 0 &gpio_n_064_077 9 0>, 483 <74 0 &gpio_n_064_077 10 0>, 484 <75 0 &gpio_n_064_077 11 0>, 485 <76 0 &gpio_n_064_077 12 0>, 486 <77 0 &gpio_n_064_077 13 0>; 487 }; 488 489 gpio_nw: gpio-northwest { 490 /* nw northwest 77 */ 491 compatible = "intel,apollo-lake-gpio"; 492 #gpio-cells = <2>; 493 gpio-map-mask = <0xffffffff 0xffffffc0>; 494 gpio-map-pass-thru = <0 0x3f>; 495 gpio-map = 496 <0 0 &gpio_nw_000_031 0 0>, 497 <1 0 &gpio_nw_000_031 1 0>, 498 <2 0 &gpio_nw_000_031 2 0>, 499 <3 0 &gpio_nw_000_031 3 0>, 500 <4 0 &gpio_nw_000_031 4 0>, 501 <5 0 &gpio_nw_000_031 5 0>, 502 <6 0 &gpio_nw_000_031 6 0>, 503 <7 0 &gpio_nw_000_031 7 0>, 504 <8 0 &gpio_nw_000_031 8 0>, 505 <9 0 &gpio_nw_000_031 9 0>, 506 <10 0 &gpio_nw_000_031 10 0>, 507 <11 0 &gpio_nw_000_031 11 0>, 508 <12 0 &gpio_nw_000_031 12 0>, 509 <13 0 &gpio_nw_000_031 13 0>, 510 <14 0 &gpio_nw_000_031 14 0>, 511 <15 0 &gpio_nw_000_031 15 0>, 512 <16 0 &gpio_nw_000_031 16 0>, 513 <17 0 &gpio_nw_000_031 17 0>, 514 <18 0 &gpio_nw_000_031 18 0>, 515 <19 0 &gpio_nw_000_031 19 0>, 516 <20 0 &gpio_nw_000_031 20 0>, 517 <21 0 &gpio_nw_000_031 21 0>, 518 <22 0 &gpio_nw_000_031 22 0>, 519 <23 0 &gpio_nw_000_031 23 0>, 520 <24 0 &gpio_nw_000_031 24 0>, 521 <25 0 &gpio_nw_000_031 25 0>, 522 <26 0 &gpio_nw_000_031 26 0>, 523 <27 0 &gpio_nw_000_031 27 0>, 524 <28 0 &gpio_nw_000_031 28 0>, 525 <29 0 &gpio_nw_000_031 29 0>, 526 <30 0 &gpio_nw_000_031 30 0>, 527 <31 0 &gpio_nw_000_031 31 0>, 528 <32 0 &gpio_nw_032_063 0 0>, 529 <33 0 &gpio_nw_032_063 1 0>, 530 <34 0 &gpio_nw_032_063 2 0>, 531 <35 0 &gpio_nw_032_063 3 0>, 532 <36 0 &gpio_nw_032_063 4 0>, 533 <37 0 &gpio_nw_032_063 5 0>, 534 <38 0 &gpio_nw_032_063 6 0>, 535 <39 0 &gpio_nw_032_063 7 0>, 536 <40 0 &gpio_nw_032_063 8 0>, 537 <41 0 &gpio_nw_032_063 9 0>, 538 <42 0 &gpio_nw_032_063 10 0>, 539 <43 0 &gpio_nw_032_063 11 0>, 540 <44 0 &gpio_nw_032_063 12 0>, 541 <45 0 &gpio_nw_032_063 13 0>, 542 <46 0 &gpio_nw_032_063 14 0>, 543 <47 0 &gpio_nw_032_063 15 0>, 544 <48 0 &gpio_nw_032_063 16 0>, 545 <49 0 &gpio_nw_032_063 17 0>, 546 <50 0 &gpio_nw_032_063 18 0>, 547 <51 0 &gpio_nw_032_063 19 0>, 548 <52 0 &gpio_nw_032_063 20 0>, 549 <53 0 &gpio_nw_032_063 21 0>, 550 <54 0 &gpio_nw_032_063 22 0>, 551 <55 0 &gpio_nw_032_063 23 0>, 552 <56 0 &gpio_nw_032_063 24 0>, 553 <57 0 &gpio_nw_032_063 25 0>, 554 <58 0 &gpio_nw_032_063 26 0>, 555 <59 0 &gpio_nw_032_063 27 0>, 556 <60 0 &gpio_nw_032_063 28 0>, 557 <61 0 &gpio_nw_032_063 29 0>, 558 <62 0 &gpio_nw_032_063 30 0>, 559 <63 0 &gpio_nw_032_063 31 0>, 560 <64 0 &gpio_nw_064_076 0 0>, 561 <65 0 &gpio_nw_064_076 1 0>, 562 <66 0 &gpio_nw_064_076 2 0>, 563 <67 0 &gpio_nw_064_076 3 0>, 564 <68 0 &gpio_nw_064_076 4 0>, 565 <69 0 &gpio_nw_064_076 5 0>, 566 <70 0 &gpio_nw_064_076 6 0>, 567 <71 0 &gpio_nw_064_076 7 0>, 568 <72 0 &gpio_nw_064_076 8 0>, 569 <73 0 &gpio_nw_064_076 9 0>, 570 <74 0 &gpio_nw_064_076 10 0>, 571 <75 0 &gpio_nw_064_076 11 0>, 572 <76 0 &gpio_nw_064_076 12 0>; 573 }; 574 575 gpio_w: gpio-west { 576 /* w west 47 */ 577 compatible = "intel,apollo-lake-gpio"; 578 #gpio-cells = <2>; 579 gpio-map-mask = <0xffffffff 0xffffffc0>; 580 gpio-map-pass-thru = <0 0x3f>; 581 gpio-map = 582 <0 0 &gpio_w_000_031 0 0>, 583 <1 0 &gpio_w_000_031 1 0>, 584 <2 0 &gpio_w_000_031 2 0>, 585 <3 0 &gpio_w_000_031 3 0>, 586 <4 0 &gpio_w_000_031 4 0>, 587 <5 0 &gpio_w_000_031 5 0>, 588 <6 0 &gpio_w_000_031 6 0>, 589 <7 0 &gpio_w_000_031 7 0>, 590 <8 0 &gpio_w_000_031 8 0>, 591 <9 0 &gpio_w_000_031 9 0>, 592 <10 0 &gpio_w_000_031 10 0>, 593 <11 0 &gpio_w_000_031 11 0>, 594 <12 0 &gpio_w_000_031 12 0>, 595 <13 0 &gpio_w_000_031 13 0>, 596 <14 0 &gpio_w_000_031 14 0>, 597 <15 0 &gpio_w_000_031 15 0>, 598 <16 0 &gpio_w_000_031 16 0>, 599 <17 0 &gpio_w_000_031 17 0>, 600 <18 0 &gpio_w_000_031 18 0>, 601 <19 0 &gpio_w_000_031 19 0>, 602 <20 0 &gpio_w_000_031 20 0>, 603 <21 0 &gpio_w_000_031 21 0>, 604 <22 0 &gpio_w_000_031 22 0>, 605 <23 0 &gpio_w_000_031 23 0>, 606 <24 0 &gpio_w_000_031 24 0>, 607 <25 0 &gpio_w_000_031 25 0>, 608 <26 0 &gpio_w_000_031 26 0>, 609 <27 0 &gpio_w_000_031 27 0>, 610 <28 0 &gpio_w_000_031 28 0>, 611 <29 0 &gpio_w_000_031 29 0>, 612 <30 0 &gpio_w_000_031 30 0>, 613 <31 0 &gpio_w_000_031 31 0>, 614 <32 0 &gpio_w_032_046 0 0>, 615 <33 0 &gpio_w_032_046 1 0>, 616 <34 0 &gpio_w_032_046 2 0>, 617 <35 0 &gpio_w_032_046 3 0>, 618 <36 0 &gpio_w_032_046 4 0>, 619 <37 0 &gpio_w_032_046 5 0>, 620 <38 0 &gpio_w_032_046 6 0>, 621 <39 0 &gpio_w_032_046 7 0>, 622 <40 0 &gpio_w_032_046 8 0>, 623 <41 0 &gpio_w_032_046 9 0>, 624 <42 0 &gpio_w_032_046 10 0>, 625 <43 0 &gpio_w_032_046 11 0>, 626 <44 0 &gpio_w_032_046 12 0>, 627 <45 0 &gpio_w_032_046 13 0>, 628 <46 0 &gpio_w_032_046 14 0>; 629 }; 630 631 gpio_sw: gpio-southwest { 632 /* sw southwest 42 */ 633 compatible = "intel,apollo-lake-gpio"; 634 #gpio-cells = <2>; 635 gpio-map-mask = <0xffffffff 0xffffffc0>; 636 gpio-map-pass-thru = <0 0x3f>; 637 gpio-map = 638 <0 0 &gpio_sw_000_031 0 0>, 639 <1 0 &gpio_sw_000_031 1 0>, 640 <2 0 &gpio_sw_000_031 2 0>, 641 <3 0 &gpio_sw_000_031 3 0>, 642 <4 0 &gpio_sw_000_031 4 0>, 643 <5 0 &gpio_sw_000_031 5 0>, 644 <6 0 &gpio_sw_000_031 6 0>, 645 <7 0 &gpio_sw_000_031 7 0>, 646 <8 0 &gpio_sw_000_031 8 0>, 647 <9 0 &gpio_sw_000_031 9 0>, 648 <10 0 &gpio_sw_000_031 10 0>, 649 <11 0 &gpio_sw_000_031 11 0>, 650 <12 0 &gpio_sw_000_031 12 0>, 651 <13 0 &gpio_sw_000_031 13 0>, 652 <14 0 &gpio_sw_000_031 14 0>, 653 <15 0 &gpio_sw_000_031 15 0>, 654 <16 0 &gpio_sw_000_031 16 0>, 655 <17 0 &gpio_sw_000_031 17 0>, 656 <18 0 &gpio_sw_000_031 18 0>, 657 <19 0 &gpio_sw_000_031 19 0>, 658 <20 0 &gpio_sw_000_031 20 0>, 659 <21 0 &gpio_sw_000_031 21 0>, 660 <22 0 &gpio_sw_000_031 22 0>, 661 <23 0 &gpio_sw_000_031 23 0>, 662 <24 0 &gpio_sw_000_031 24 0>, 663 <25 0 &gpio_sw_000_031 25 0>, 664 <26 0 &gpio_sw_000_031 26 0>, 665 <27 0 &gpio_sw_000_031 27 0>, 666 <28 0 &gpio_sw_000_031 28 0>, 667 <29 0 &gpio_sw_000_031 29 0>, 668 <30 0 &gpio_sw_000_031 30 0>, 669 <31 0 &gpio_sw_000_031 31 0>, 670 <32 0 &gpio_sw_032_042 0 0>, 671 <33 0 &gpio_sw_032_042 1 0>, 672 <34 0 &gpio_sw_032_042 2 0>, 673 <35 0 &gpio_sw_032_042 3 0>, 674 <36 0 &gpio_sw_032_042 4 0>, 675 <37 0 &gpio_sw_032_042 5 0>, 676 <38 0 &gpio_sw_032_042 6 0>, 677 <39 0 &gpio_sw_032_042 7 0>, 678 <40 0 &gpio_sw_032_042 8 0>, 679 <41 0 &gpio_sw_032_042 9 0>, 680 <42 0 &gpio_sw_032_042 10 0>; 681 }; 682}; 683
