1/*
2 * Copyright 2018 Foundries.io Ltd
3 * SPDX-License-Identifier: Apache-2.0
4 */
5
6#include <riscv/openisa/rv32m1.dtsi>
7
8/ {
9	aliases {
10		intmux = &intmux0;
11		system-lptmr = &lptmr0;
12	};
13
14	cpus {
15		/delete-node/ cpu@1;
16	};
17};
18
19&m4_flash {
20	partitions {
21		compatible = "fixed-partitions";
22		#address-cells = <1>;
23		#size-cells = <1>;
24
25		/* This configuration assumes the Arm cores are disabled, as
26		 * these base addresses contain the Arm core vector tables if
27		 * they are used.
28		 */
29
30		ri5cy_code_partition: partition@0 {
31			reg = <0x00000000 0x000fff00>;
32		};
33
34		ri5cy_vector_partition: partition@fff00 {
35			reg = <0x000fff00 0x100>;
36		};
37	};
38};
39
40/*
41 * INTMUX channels below are somewhat arbitrary.
42 *
43 * The system timer (assumed at LPTMR0) is placed on channel 0, and peripherals
44 * are in channel 1. This can be overridden with overlays, e.g. to manage IRQ
45 * priorities, and it will Just Work, but using fewer channels here allows
46 * disabling unused ones in Kconfig, making the binary smaller.
47 *
48 * Each enabled channel requires 256 bytes in _sw_isr_table, so the savings for
49 * disabling channels can add up.
50 */
51
52&intmux0 {
53	status = "okay";
54};
55
56&intmux0_ch0 {
57	interrupt-parent = <&event0>;
58	status = "okay";
59};
60
61&intmux0_ch1 {
62	interrupt-parent = <&event0>;
63	status = "okay";
64};
65
66&intmux0_ch2 {
67	interrupt-parent = <&event0>;
68};
69
70&intmux0_ch3 {
71	interrupt-parent = <&event0>;
72};
73
74&intmux0_ch4 {
75	interrupt-parent = <&event0>;
76};
77
78&intmux0_ch5 {
79	interrupt-parent = <&event0>;
80};
81
82&intmux0_ch6 {
83	interrupt-parent = <&event0>;
84};
85
86&intmux0_ch7 {
87	interrupt-parent = <&event0>;
88};
89
90/delete-node/ &intmux1;
91
92&lptmr0 {
93	interrupt-parent = <&intmux0_ch0>;
94	interrupts = <7>;
95};
96
97&lptmr1 {
98	interrupt-parent = <&intmux0_ch1>;
99	interrupts = <8>;
100};
101
102&lptmr2 {
103	interrupt-parent = <&intmux0_ch1>;
104	interrupts = <22>;
105};
106
107&gpioa {
108	interrupt-parent = <&event0>;
109	interrupts = <18>;
110};
111
112&gpiob {
113	interrupt-parent = <&intmux0_ch1>;
114	interrupts = <15>;
115};
116
117&gpioc {
118	interrupt-parent = <&intmux0_ch1>;
119	interrupts = <16>;
120};
121
122&gpiod {
123	interrupt-parent = <&intmux0_ch1>;
124	interrupts = <17>;
125};
126
127&gpioe {
128	interrupt-parent = <&intmux0_ch1>;
129	interrupts = <27>;
130};
131
132&lpuart0 {
133	interrupt-parent = <&event0>;
134	interrupts = <17>;
135};
136
137&lpuart1 {
138	interrupt-parent = <&intmux0_ch1>;
139	interrupts = <13>;
140};
141
142&lpuart2 {
143	interrupt-parent = <&intmux0_ch1>;
144	interrupts = <14>;
145};
146
147&lpuart3 {
148	interrupt-parent = <&intmux0_ch1>;
149	interrupts = <26>;
150};
151
152&lpi2c0 {
153	interrupt-parent = <&event0>;
154	interrupts = <15>;
155};
156
157&lpi2c1 {
158	interrupt-parent = <&event0>;
159	interrupts = <16>;
160};
161
162&lpi2c2 {
163	interrupt-parent = <&intmux0_ch1>;
164	interrupts = <11>;
165};
166
167&lpi2c3 {
168	interrupt-parent = <&intmux0_ch1>;
169	interrupts = <24>;
170};
171
172&lpspi0 {
173	interrupt-parent = <&event0>;
174	interrupts = <13>;
175};
176
177&lpspi1 {
178	interrupt-parent = <&event0>;
179	interrupts = <14>;
180};
181
182&lpspi2 {
183	interrupt-parent = <&intmux0_ch1>;
184	interrupts = <12>;
185};
186
187&lpspi3 {
188	interrupt-parent = <&intmux0_ch1>;
189	interrupts = <25>;
190};
191
192&generic_fsk {
193	interrupt-parent = <&intmux0_ch1>;
194	interrupts = <29>;
195};
196
197&tpm0 {
198	interrupt-parent = <&event0>;
199	interrupts = <19>;
200};
201
202&tpm1 {
203	interrupt-parent = <&intmux0_ch1>;
204	interrupts = <9>;
205};
206
207&tpm2 {
208	interrupt-parent = <&intmux0_ch1>;
209	interrupts = <10>;
210};
211
212&tpm3 {
213	interrupt-parent = <&intmux0_ch1>;
214	interrupts = <23>;
215};
216
217&trng {
218	interrupt-parent = <&intmux0_ch1>;
219	interrupts = <20>;
220};
221