1/*
2 * Copyright (C) 2023, Intel Corporation
3 *
4 * SPDX-License-Identifier: Apache-2.0
5 */
6
7/dts-v1/;
8
9#include <skeleton.dtsi>
10
11/ {
12	#address-cells = <1>;
13	#size-cells = <1>;
14
15	cpus {
16		#address-cells = <1>;
17		#size-cells = <0>;
18		cpu0: cpu@0 {
19			device_type = "cpu";
20			compatible = "intel,niosv";
21			riscv,isa = "rv32ima_zicsr_zifencei";
22			reg = <0>;
23			clock-frequency = <50000000>;
24
25			/* Platform interrupts IRQs index start from 16 */
26			intc: interrupt-controller {
27				compatible = "riscv,cpu-intc";
28				#address-cells = <0>;
29				#interrupt-cells = <1>;
30				interrupt-controller;
31			};
32		};
33	};
34
35	soc {
36		#address-cells = <1>;
37		#size-cells = <1>;
38		compatible = "intel,niosv-g-soc", "simple-bus";
39		interrupt-parent = <&intc>;
40		ranges;
41
42		sram0: memory@0 {
43			compatible = "mmio-sram";
44		};
45
46		mtimer: machine-timer@90000 {
47			compatible = "niosv-machine-timer";
48			reg = <0x90000 0x10>;
49			interrupts = <7>;
50		};
51
52		uart0: serial@90078 {
53			compatible = "altr,jtag-uart";
54			interrupts = <16>;
55			status = "disabled";
56		};
57	};
58};
59