1/*
2 * Copyright (c) 2021 Henrik Brix Andersen <henrik@brixandersen.dk>
3 *
4 * SPDX-License-Identifier: Apache-2.0
5 */
6
7/dts-v1/;
8
9#include <skeleton.dtsi>
10#include <zephyr/dt-bindings/gpio/gpio.h>
11
12/ {
13	chosen {
14		zephyr,entropy = &trng;
15	};
16
17	cpus {
18		#address-cells = <1>;
19		#size-cells = <0>;
20
21		cpu0: cpu@0 {
22			compatible = "neorv32-cpu";
23			riscv,isa = "rv32imc_zicsr";
24			reg = <0>;
25			device_type = "cpu";
26
27			intc: interrupt-controller {
28				compatible = "riscv,cpu-intc";
29				interrupt-controller;
30				#address-cells = <1>;
31				#interrupt-cells = <1>;
32
33				firq: firq {
34					#address-cells = <1>;
35					interrupt-map-mask = <0x0 0xffffffff>;
36					interrupt-map = <
37						0  0 &intc 0 16
38						0  1 &intc 0 17
39						0  2 &intc 0 18
40						0  3 &intc 0 19
41						0  4 &intc 0 20
42						0  5 &intc 0 21
43						0  6 &intc 0 22
44						0  7 &intc 0 23
45						0  8 &intc 0 24
46						0  9 &intc 0 25
47						0 10 &intc 0 26
48						0 11 &intc 0 27
49						0 12 &intc 0 28
50						0 13 &intc 0 29
51						0 14 &intc 0 30
52						0 15 &intc 0 31
53					>;
54					#interrupt-cells = <1>;
55				};
56			};
57		};
58	};
59
60	soc {
61		compatible = "simple-bus";
62		interrupt-parent = <&firq>;
63		#address-cells = <1>;
64		#size-cells = <1>;
65		ranges;
66
67		mtimer: timer@ffffff90 {
68			compatible = "neorv32-machine-timer";
69			reg = <0xffffff90 0x10>;
70			interrupts = <7>;
71		};
72
73		uart0: serial@ffffffa0 {
74			compatible = "neorv32-uart";
75			status = "disabled";
76			reg = <0xffffffa0 8>;
77			interrupts = <2>, <3>;
78			interrupt-names = "RX", "TX";
79			syscon = <&sysinfo>;
80		};
81
82		trng: rng@ffffffb8 {
83			compatible = "neorv32-trng";
84			status = "disabled";
85			reg = <0xffffffb8 4>;
86			syscon = <&sysinfo>;
87		};
88
89		gpio: gpio {
90			compatible = "simple-bus";
91			gpio-map-mask = <0xffffffe0 0xffffffc0>;
92			gpio-map-pass-thru = <0x1f 0x3f>;
93			gpio-map = <
94				0x00 0x0 &gpio_lo 0x0 0x0
95				0x20 0x0 &gpio_hi 0x0 0x0
96			>;
97			#gpio-cells = <2>;
98			#address-cells = <1>;
99			#size-cells = <1>;
100			ranges;
101
102			gpio_lo: gpio@ffffffc0 {
103				compatible = "neorv32-gpio";
104				status = "disabled";
105				reg = <0xffffffc0 4 0xffffffc8 4>;
106				reg-names = "input", "output";
107				gpio-controller;
108				ngpios = <32>;
109				syscon = <&sysinfo>;
110				#gpio-cells = <2>;
111			};
112
113			gpio_hi: gpio@ffffffc4 {
114				compatible = "neorv32-gpio";
115				status = "disabled";
116				reg = <0xffffffc4 4 0xffffffcc 4>;
117				reg-names = "input", "output";
118				gpio-controller;
119				ngpios = <32>;
120				syscon = <&sysinfo>;
121				#gpio-cells = <2>;
122			};
123		};
124
125		uart1: serial@ffffffd0 {
126			compatible = "neorv32-uart";
127			status = "disabled";
128			reg = <0xffffffd0 8>;
129			interrupts = <4>, <5>;
130			interrupt-names = "RX", "TX";
131			syscon = <&sysinfo>;
132		};
133
134		sysinfo: syscon@ffffffe0 {
135			compatible = "neorv-sysinfo", "syscon";
136			status = "okay";
137			reg = <0xffffffe0 32>;
138		};
139	};
140};
141