1/* SPDX-License-Identifier: Apache-2.0 */
2
3#include "skeleton.dtsi"
4#include <zephyr/dt-bindings/i2c/i2c.h>
5
6/ {
7	cpus {
8		#address-cells = <1>;
9		#size-cells = <0>;
10
11		cpu: cpu@0 {
12			device_type = "cpu";
13			compatible = "altr,nios2f";
14			reg = <0>;
15			interrupt-controller;
16			#interrupt-cells = <1>;
17		};
18	};
19
20	flash0: flash@0 {
21		compatible = "soc-nv-flash";
22		reg = <0x00 0xb8000>;
23	};
24
25	sram0: memory@400000 {
26		compatible = "mmio-sram";
27		reg = <0x400000 0x20000>;
28	};
29
30	soc {
31		#address-cells = <1>;
32		#size-cells = <1>;
33		compatible = "simple-bus";
34		interrupt-parent = <&cpu>;
35		ranges;
36
37		uart0: uart@100000 {
38			compatible = "ns16550";
39			reg = <0x100000 0x400>;
40			clock-frequency = <50000000>;
41			interrupts = <1 0>;
42			reg-shift = <2>;
43			status = "disabled";
44		};
45
46		jtag_uart: uart@201000 {
47			compatible = "altr,jtag-uart";
48			reg = <0x201000 0x8>;
49
50			status = "disabled";
51		};
52
53		i2c0: i2c@100200 {
54			compatible = "altr,nios2-i2c";
55			clock-frequency = <I2C_BITRATE_ULTRA>;
56			#address-cells = <1>;
57			#size-cells = <0>;
58			reg = <0x100200 0x400>;
59			interrupts = <4 10>;
60		};
61
62		dma: dma@100200 {
63			compatible = "altr,msgdma";
64			reg = <0x1002c0 0x30>;
65			interrupts = <3 3>;
66			#dma-cells = <0>;
67		};
68
69
70		qspi: qspi@100240 {
71			compatible = "altr,nios2-qspi";
72			#address-cells = <1>;
73			#size-cells = <0>;
74			reg = <0x100240 0x40>, <0x8000000 0x4000000>;
75			reg-names = "qspi", "qspi_mm";
76			status = "disabled";
77		};
78	};
79};
80