1# Copyright (c) 2018, NXP
2# SPDX-License-Identifier: Apache-2.0
3
4description: NXP Kinetis DSPI controller
5
6compatible: "nxp,kinetis-dspi"
7
8include: ["spi-controller.yaml", "pinctrl-device.yaml"]
9
10properties:
11  reg:
12    required: true
13
14  interrupts:
15    required: true
16
17  clocks:
18    required: true
19
20  pcs-sck-delay:
21    type: int
22    description: |
23      Delay in nanoseconds from the chip select assert to the first clock
24      edge. If not set, the minimum supported delay is used.
25
26  sck-pcs-delay:
27    type: int
28    description: |
29      Delay in nanoseconds from the last clock edge to the chip select
30      deassert. If not set, the minimum supported delay is used.
31
32  transfer-delay:
33    type: int
34    description: |
35      Delay in nanoseconds from the chip select deassert to the next chip
36      select assert. If not set, the minimum supported delay is used.
37
38  pinctrl-0:
39    required: true
40
41  nxp,rx-tx-chn-share:
42    type: boolean
43    description: If the edma channel shared with tx and rx
44
45  ctar:
46    type: int
47    description: |
48      ctar register selection range form 0-1 for master mode, 0 for slave mode
49
50  sample-point:
51    type: int
52    description: |
53      Controls when the DSPI master samples SIN in the Modified Transfer Format.
54      This field is valid only when the CPHA bit in the CTAR register is 0.
55
56  continuous-sck:
57    type: boolean
58    description: |
59      continuous SCK enable. Note that the continuous SCK is only
60      supported for CPHA = 1.
61
62  rx-fifo-overwrite:
63    type: boolean
64    description: |
65      receive FIFO overflow overwrite enable. If ROOE = 0, the incoming
66      data is ignored and the data from the transfer that generated the overflow
67      is also ignored. If ROOE = 1, the incoming data is shifted to the
68      shift register.
69
70  modified-timing-format:
71    type: boolean
72    description: |
73      Enables a modified transfer format to be used if true.
74
75  tx-fifo-size:
76    type: int
77    description: |
78      tx fifo size
79
80  rx-fifo-size:
81    type: int
82    description: |
83      rx fifo size
84