1# Copyright (c) 2020 Hubert Miś <hubert.mis@gmail.com>
2# SPDX-License-Identifier: Apache-2.0
3
4description: FTDI FT800 graphic controller
5
6compatible: "ftdi,ft800"
7
8include: spi-device.yaml
9
10properties:
11  irq-gpios:
12    type: phandle-array
13    description: Optional IRQ line of FT800 controller
14
15  pclk:
16    type: int
17    required: true
18    description: |
19      The value to divide the main clock by for PCLK. If the
20      typical main clock was 48MHz and this value is 5, the PCLK
21      will be 9.6 MHz. Must be positive value to enable the screen
22
23  pclk_pol:
24    type: int
25    required: true
26    description: |
27      Polarity of PCLK. If it is set to zero, PCLK polarity is on
28      the rising edge. If it is set to one, PCLK polarity is on
29      the falling edge.
30
31  cspread:
32    type: int
33    required: true
34    description: |
35      Controls the transition of RGB signals with PCLK active clock
36      edge. When set to 0, R[7:2],G[7:2] and B[7:2] signals change
37      following the active edge of PCLK. When set to 1, R[7:2]
38      changes a PCLK clock early and B[7:2] a PCLK clock later,
39      which helps reduce the system noise.
40
41  swizzle:
42    type: int
43    required: true
44    description: |
45      Controls the arrangement of output RGB pins, which may help
46      support different LCD panel. Please check FT800 Programmers
47      Guide for details.
48
49  vsize:
50    type: int
51    required: true
52    description: Number of visible lines of pixels in one frame
53
54  voffset:
55    type: int
56    required: true
57    description: Number of invisible lines at the beginning of a new frame
58
59  vcycle:
60    type: int
61    required: true
62    description: |
63      Number of all lines in a frame. It includes all visible and
64      invisible lines at the beginning and at the end of a frame.
65
66  vsync0:
67    type: int
68    required: true
69    description: |
70      Number of lines for the high state of signal VSYNC at
71      the start of new frame.
72
73  vsync1:
74    type: int
75    required: true
76    description: |
77      Number of lines for signal VSYNC toggle takes at the start
78      of new frame.
79
80  hsize:
81    type: int
82    required: true
83    description: Number of PCLK cycles per visible part of horizontal line
84
85  hoffset:
86    type: int
87    required: true
88    description: |
89      Number of PCLK cycles before pixels are scanned out for
90      given line
91
92  hcycle:
93    type: int
94    required: true
95    description: Number of total PCLK cycles per horizontal line scan.
96
97  hsync0:
98    type: int
99    required: true
100    description: Number of PCLK cycles of HSYNC high state during start of
101      line
102
103  hsync1:
104    type: int
105    required: true
106    description: Number of PCLK cycles for HSYNC toggle during start of line.
107