1/*
2 * Copyright 2022 NXP
3 *
4 * SPDX-License-Identifier: Apache-2.0
5 */
6
7#include <mem.h>
8#include <freq.h>
9#include <arm64/armv8-a.dtsi>
10#include <zephyr/dt-bindings/clock/imx_ccm.h>
11#include <zephyr/dt-bindings/interrupt-controller/arm-gic.h>
12
13/ {
14	#address-cells = <1>;
15	#size-cells = <1>;
16
17	chosen {
18		zephyr,console = &uart2;
19		zephyr,shell-uart = &uart2;
20		zephyr,sram = &sram0;
21	};
22
23	cpus {
24		#address-cells = <1>;
25		#size-cells = <0>;
26
27		cpu@0 {
28			device_type = "cpu";
29			compatible = "arm,cortex-a55";
30			reg = <0>;
31		};
32
33		cpu@100 {
34			device_type = "cpu";
35			compatible = "arm,cortex-a55";
36			reg = <0x100>;
37		};
38
39	};
40
41	arch_timer: timer {
42		compatible = "arm,armv8-timer";
43		interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL
44			      IRQ_DEFAULT_PRIORITY>,
45			     <GIC_PPI 14 IRQ_TYPE_LEVEL
46			      IRQ_DEFAULT_PRIORITY>,
47			     <GIC_PPI 11 IRQ_TYPE_LEVEL
48			      IRQ_DEFAULT_PRIORITY>,
49			     <GIC_PPI 10 IRQ_TYPE_LEVEL
50			      IRQ_DEFAULT_PRIORITY>;
51		interrupt-parent = <&gic>;
52	};
53
54	gic: interrupt-controller@48000000 {
55		compatible = "arm,gic-v3", "arm,gic";
56		reg = <0x48000000 0x10000>, /* GIC Dist */
57		      <0x48040000 0xc0000>; /* GICR (RD_base + SGI_base) */
58		interrupt-controller;
59		#interrupt-cells = <4>;
60		status = "okay";
61	};
62
63	iomuxc: iomuxc@443c0000 {
64		compatible = "nxp,imx-iomuxc";
65		reg = <0x443c0000 DT_SIZE_K(64)>;
66		status = "okay";
67		pinctrl: pinctrl {
68			status = "okay";
69			compatible = "nxp,imx93-pinctrl";
70		};
71	};
72
73	ana_pll: ana_pll@44480000 {
74		compatible = "nxp,imx-ana";
75		reg = <0x44480000 DT_SIZE_K(64)>;
76	};
77
78	ccm: ccm@44450000 {
79		compatible = "nxp,imx-ccm";
80		reg = <0x44450000 DT_SIZE_K(64)>;
81		#clock-cells = <3>;
82	};
83
84	lpuart1: serial@44380000 {
85		compatible = "nxp,imx-lpuart", "nxp,kinetis-lpuart";
86		reg = <0x44380000 DT_SIZE_K(64)>;
87		interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>;
88		interrupt-names = "irq_0";
89		interrupt-parent = <&gic>;
90		clocks = <&ccm IMX_CCM_LPUART_CLK 0x6c 24>;
91		status = "disabled";
92	};
93
94	lpuart2: serial@44390000 {
95		compatible = "nxp,imx-lpuart", "nxp,kinetis-lpuart";
96		reg = <0x44390000 DT_SIZE_K(64)>;
97		interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>;
98		interrupt-names = "irq_0";
99		interrupt-parent = <&gic>;
100		clocks = <&ccm IMX_CCM_LPUART_CLK 0x6c 24>;
101		status = "disabled";
102	};
103};
104