1/*
2 * Copyright 2020-2022 NXP
3 *
4 * SPDX-License-Identifier: Apache-2.0
5 */
6
7#include <mem.h>
8#include <freq.h>
9#include <arm64/armv8-a.dtsi>
10#include <zephyr/dt-bindings/clock/imx_ccm.h>
11#include <zephyr/dt-bindings/interrupt-controller/arm-gic.h>
12
13/ {
14	#address-cells = <1>;
15	#size-cells = <1>;
16
17	cpus {
18		#address-cells = <1>;
19		#size-cells = <0>;
20
21		cpu@0 {
22			device_type = "cpu";
23			compatible = "arm,cortex-a53";
24			reg = <0>;
25		};
26
27		cpu@1 {
28			device_type = "cpu";
29			compatible = "arm,cortex-a53";
30			reg = <1>;
31		};
32
33		cpu@2 {
34			device_type = "cpu";
35			compatible = "arm,cortex-a53";
36			reg = <2>;
37		};
38
39		cpu@3 {
40			device_type = "cpu";
41			compatible = "arm,cortex-a53";
42			reg = <3>;
43		};
44	};
45
46	arch_timer: timer {
47		compatible = "arm,armv8-timer";
48		interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL
49			      IRQ_DEFAULT_PRIORITY>,
50			     <GIC_PPI 14 IRQ_TYPE_LEVEL
51			      IRQ_DEFAULT_PRIORITY>,
52			     <GIC_PPI 11 IRQ_TYPE_LEVEL
53			      IRQ_DEFAULT_PRIORITY>,
54			     <GIC_PPI 10 IRQ_TYPE_LEVEL
55			      IRQ_DEFAULT_PRIORITY>;
56		interrupt-parent = <&gic>;
57	};
58
59	gic: interrupt-controller@38800000 {
60		compatible = "arm,gic-v3", "arm,gic";
61		reg = <0x38800000 0x10000>, /* GIC Dist */
62		      <0x38880000 0xc0000>; /* GICR (RD_base + SGI_base) */
63		interrupt-controller;
64		#interrupt-cells = <4>;
65		status = "okay";
66	};
67
68	soc {
69		ana_pll: ana_pll@30360000 {
70			compatible = "nxp,imx-ana";
71			reg = <0x30360000 DT_SIZE_K(64)>;
72		};
73
74		ccm: ccm@30380000 {
75			compatible = "nxp,imx-ccm";
76			reg = <0x30380000 DT_SIZE_K(64)>;
77			#clock-cells = <3>;
78		};
79
80		uart2: uart@30890000 {
81			compatible = "nxp,imx-iuart";
82			reg = <0x30890000 DT_SIZE_K(64)>;
83			interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>;
84			interrupt-names = "irq_0";
85			interrupt-parent = <&gic>;
86			clocks = <&ccm IMX_CCM_UART2_CLK 0x6c 24>;
87			status = "disabled";
88		};
89
90		uart4: uart@30a60000 {
91			compatible = "nxp,imx-iuart";
92			reg = <0x30a60000 DT_SIZE_K(64)>;
93			interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>;
94			interrupt-names = "irq_0";
95			interrupt-parent = <&gic>;
96			clocks = <&ccm IMX_CCM_UART4_CLK 0x6c 24>;
97			status = "disabled";
98		};
99
100		iomuxc: iomuxc@30330000 {
101			compatible = "nxp,imx-iomuxc";
102			reg = <0x30330000 DT_SIZE_K(64)>;
103			status = "okay";
104			pinctrl: pinctrl {
105				status = "okay";
106				compatible = "nxp,imx8mp-pinctrl";
107			};
108		};
109	};
110};
111