1/*
2 * Copyright 2020-2022 NXP
3 *
4 * SPDX-License-Identifier: Apache-2.0
5 */
6
7#include <mem.h>
8#include <freq.h>
9#include <arm64/armv8-a.dtsi>
10#include <zephyr/dt-bindings/clock/imx_ccm.h>
11#include <zephyr/dt-bindings/interrupt-controller/arm-gic.h>
12
13/ {
14	#address-cells = <1>;
15	#size-cells = <1>;
16
17	chosen {
18		zephyr,console = &uart2;
19		zephyr,shell-uart = &uart2;
20		zephyr,sram = &sram0;
21	};
22
23	cpus {
24		#address-cells = <1>;
25		#size-cells = <0>;
26
27		cpu@0 {
28			device_type = "cpu";
29			compatible = "arm,cortex-a53";
30			reg = <0>;
31		};
32
33		cpu@1 {
34			device_type = "cpu";
35			compatible = "arm,cortex-a53";
36			reg = <1>;
37		};
38
39		cpu@2 {
40			device_type = "cpu";
41			compatible = "arm,cortex-a53";
42			reg = <2>;
43		};
44
45		cpu@3 {
46			device_type = "cpu";
47			compatible = "arm,cortex-a53";
48			reg = <3>;
49		};
50
51	};
52
53	arch_timer: timer {
54		compatible = "arm,armv8-timer";
55		interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL
56			      IRQ_DEFAULT_PRIORITY>,
57			     <GIC_PPI 14 IRQ_TYPE_LEVEL
58			      IRQ_DEFAULT_PRIORITY>,
59			     <GIC_PPI 11 IRQ_TYPE_LEVEL
60			      IRQ_DEFAULT_PRIORITY>,
61			     <GIC_PPI 10 IRQ_TYPE_LEVEL
62			      IRQ_DEFAULT_PRIORITY>;
63		interrupt-parent = <&gic>;
64	};
65
66	gic: interrupt-controller@38800000 {
67		compatible = "arm,gic-v3", "arm,gic";
68		reg = <0x38800000 0x10000>, /* GIC Dist */
69		      <0x38880000 0xc0000>; /* GICR (RD_base + SGI_base) */
70		interrupt-controller;
71		#interrupt-cells = <4>;
72		status = "okay";
73	};
74
75	iomuxc: iomuxc@30330000 {
76		compatible = "nxp,imx-iomuxc";
77		reg = <0x30330000 DT_SIZE_K(64)>;
78		status = "okay";
79		pinctrl: pinctrl {
80			status = "okay";
81			compatible = "nxp,imx8m-pinctrl";
82		};
83	};
84
85	ana_pll: ana_pll@30360000 {
86		compatible = "nxp,imx-ana";
87		reg = <0x30360000 DT_SIZE_K(64)>;
88	};
89
90	ccm: ccm@30380000 {
91		compatible = "nxp,imx-ccm";
92		reg = <0x30380000 DT_SIZE_K(64)>;
93		#clock-cells = <3>;
94	};
95
96	uart2: serial@30890000 {
97		compatible = "nxp,imx-iuart";
98		reg = <0x30890000 DT_SIZE_K(64)>;
99		interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>;
100		interrupt-names = "irq_0";
101		interrupt-parent = <&gic>;
102		clocks = <&ccm IMX_CCM_UART2_CLK 0x6c 24>;
103		status = "disabled";
104	};
105
106	uart4: serial@30a60000 {
107		compatible = "nxp,imx-iuart";
108		reg = <0x30a60000 DT_SIZE_K(64)>;
109		interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>;
110		interrupt-names = "irq_0";
111		interrupt-parent = <&gic>;
112		clocks = <&ccm IMX_CCM_UART4_CLK 0x6c 24>;
113		status = "disabled";
114	};
115};
116