1/*
2 * Copyright 2023 honglin leng <a909204013@gmail.com>
3 *
4 * SPDX-License-Identifier: Apache-2.0
5 */
6
7#include <arm64/armv8-a.dtsi>
8#include <zephyr/dt-bindings/interrupt-controller/arm-gic.h>
9
10/ {
11	cpus {
12		#address-cells = <1>;
13		#size-cells = <0>;
14
15		cpu@0 {
16			device_type = "cpu";
17			compatible = "arm,cortex-a72";
18			reg = <0>;
19		};
20	};
21
22	timer {
23		compatible = "arm,armv8-timer";
24		interrupt-parent = <&gic>;
25		interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL
26			      IRQ_DEFAULT_PRIORITY>,
27			     <GIC_PPI 14 IRQ_TYPE_LEVEL
28			      IRQ_DEFAULT_PRIORITY>,
29			     <GIC_PPI 11 IRQ_TYPE_LEVEL
30			      IRQ_DEFAULT_PRIORITY>,
31			     <GIC_PPI 10 IRQ_TYPE_LEVEL
32			      IRQ_DEFAULT_PRIORITY>;
33	};
34
35	soc {
36		sram0: memory@200000 {
37			device_type = "memory";
38			compatible = "mmio-sram";
39			reg = <0x200000 0x80000>;
40		};
41
42		gic: interrupt-controller@ff841000 {
43			compatible = "arm,gic-v2", "arm,gic";
44			reg = <0xff841000 0x1000>,
45			      <0xff842000 0x2000>;
46			interrupt-controller;
47			#interrupt-cells = <4>;
48			status = "okay";
49		};
50
51		uart1: uart@fe215040 {
52			compatible = "brcm,bcm2711-aux-uart";
53			reg = <0xfe215040 0x40>;
54			clock-frequency = <500000000>;
55			interrupt-parent = <&gic>;
56			interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL
57				IRQ_DEFAULT_PRIORITY>;
58			status = "disabled";
59		};
60	};
61};
62