1/* SPDX-License-Identifier: Apache-2.0 */
2
3#include <arm/armv7-m.dtsi>
4
5#include <zephyr/dt-bindings/adc/adc.h>
6#include <zephyr/dt-bindings/i2c/i2c.h>
7#include <zephyr/dt-bindings/gpio/gpio.h>
8
9#define INT_UARTA0              21          // UART0 Rx and Tx
10#define INT_UARTA1              22          // UART1 Rx and Tx
11#define INT_I2CA0               24          // I2C controller
12#define INT_ADCCH0              30          // ADC channel 0
13#define INT_ADCCH1              31          // ADC channel 1
14#define INT_ADCCH2              32          // ADC channel 2
15#define INT_ADCCH3              33          // ADC channel 3
16#define INT_WDT                 34          // Watchdog Timer
17
18/* Note: Zephyr uses exception numbers, vs the IRQ #s used by the CC32XX SDK */
19/* which are offset by 16: */
20#define EXP_UARTA0 (INT_UARTA0 - 16)
21#define EXP_UARTA1 (INT_UARTA1 - 16)
22#define EXP_I2CA0  (INT_I2CA0 - 16)
23#define EXP_ADCCH0 (INT_ADCCH0 - 16)
24#define EXP_ADCCH1 (INT_ADCCH1 - 16)
25#define EXP_ADCCH2 (INT_ADCCH2 - 16)
26#define EXP_ADCCH3 (INT_ADCCH3 - 16)
27#define EXP_WDT    (INT_WDT - 16)
28#define EXC_GPIOA0  0  /* (INT_GPIOA0 - 16) = (16-16) */
29#define EXC_GPIOA1  1  /* (INT_GPIOA1 - 16) = (17-16) */
30#define EXC_GPIOA2  2  /* (INT_GPIOA2 - 16) = (18-16) */
31#define EXC_GPIOA3  3  /* (INT_GPIOA3 - 16) = (19-16) */
32
33/ {
34	cpus {
35		#address-cells = <1>;
36		#size-cells = <0>;
37
38		cpu@0 {
39			device_type = "cpu";
40			compatible = "arm,cortex-m4";
41			reg = <0>;
42		};
43	};
44
45	sram0: memory@20000000 {
46		compatible = "mmio-sram";
47	};
48
49	flash0: serial-flash@0 {
50		compatible = "serial-flash";
51	};
52
53	sysclk: system-clock {
54		compatible = "fixed-clock";
55		clock-frequency = <80000000>;
56		#clock-cells = <0>;
57	};
58
59	soc {
60		uart0: uart@4000c000 {
61			compatible = "ti,cc32xx-uart";
62			reg = <0x4000c000 0x4c>;
63			interrupts = <EXP_UARTA0 3>;
64			clocks = <&sysclk>;
65			status = "disabled";
66		};
67
68		uart1: uart@4000d000 {
69			compatible = "ti,cc32xx-uart";
70			reg = <0x4000d000 0x4c>;
71			interrupts = <EXP_UARTA1 3>;
72			clocks = <&sysclk>;
73			status = "disabled";
74		};
75
76		i2c0: i2c@40020000 {
77			compatible = "ti,cc32xx-i2c";
78			clocks = <&sysclk>;
79			clock-frequency = <I2C_BITRATE_STANDARD>;
80			#address-cells = <1>;
81			#size-cells = <0>;
82			reg = <0x40020000 0xfc8>;
83			interrupts = <EXP_I2CA0 3>;
84			status = "disabled";
85		};
86
87		gpioa0: gpio@40004000 {
88			compatible = "ti,cc32xx-gpio";
89			reg = <0x40004000 0x1000>;
90			interrupts = <0 1>;
91			gpio-controller;
92			#gpio-cells = <2>;
93		};
94
95		gpioa1: gpio@40005000 {
96			compatible = "ti,cc32xx-gpio";
97			reg = <0x40005000 0x1000>;
98			interrupts = <1 1>;
99			gpio-controller;
100			#gpio-cells = <2>;
101		};
102
103		gpioa2: gpio@40006000 {
104			compatible = "ti,cc32xx-gpio";
105			reg = <0x40006000 0x1000>;
106			interrupts = <2 1>;
107			gpio-controller;
108			#gpio-cells = <2>;
109		};
110
111		gpioa3: gpio@40007000 {
112			compatible = "ti,cc32xx-gpio";
113			reg = <0x40007000 0x1000>;
114			interrupts = <3 1>;
115			gpio-controller;
116			#gpio-cells = <2>;
117		};
118
119		adc0: adc@4402e800 {
120			compatible = "ti,cc32xx-adc";
121			reg = <0x4402E800 0x100>;
122			interrupts = <EXP_ADCCH0 3>, <EXP_ADCCH1 3>, <EXP_ADCCH2 3>, <EXP_ADCCH3 3>;
123			status = "disabled";
124			#io-channel-cells = <1>;
125		};
126
127		wdt0: watchdog@40000000 {
128			compatible = "ti,cc32xx-watchdog";
129			reg = <0x40000000 0x1000>;
130			interrupts = <EXP_WDT 0>;
131			status = "disabled";
132		};
133
134		pinctrl: pin-controller@4402e0a0 {
135			compatible = "ti,cc32xx-pinctrl";
136			reg = <0x4402e0a0 0x80>;
137		};
138	};
139};
140
141&nvic {
142	arm,num-irq-priority-bits = <3>;
143};
144