1/* 2 * Copyright (c) 2019 Brett Witherspoon 3 * 4 * SPDX-License-Identifier: Apache-2.0 5 */ 6 7#include <arm/armv7-m.dtsi> 8#include <zephyr/dt-bindings/adc/adc.h> 9#include <zephyr/dt-bindings/i2c/i2c.h> 10#include <zephyr/dt-bindings/gpio/gpio.h> 11#include <zephyr/dt-bindings/pwm/pwm.h> 12 13/ { 14 chosen { 15 zephyr,entropy = &trng; 16 zephyr,flash-controller = &flash_controller; 17 }; 18 19 cpus { 20 #address-cells = <1>; 21 #size-cells = <0>; 22 23 cpu0: cpu@0 { 24 device_type = "cpu"; 25 compatible = "arm,cortex-m4"; 26 reg = <0>; 27 cpu-power-states = <&idle &standby>; 28 }; 29 30 power-states { 31 idle: idle { 32 compatible = "zephyr,power-state"; 33 power-state-name = "suspend-to-idle"; 34 min-residency-us = <1000>; 35 }; 36 37 standby: standby { 38 compatible = "zephyr,power-state"; 39 power-state-name = "standby"; 40 min-residency-us = <5000>; 41 exit-latency-us = <240>; 42 }; 43 }; 44 }; 45 46 sram0: memory@20000000 { 47 compatible = "mmio-sram"; 48 }; 49 50 /* VIMS RAM configurable in CCFG as GPRAM or cache for FLASH (default) */ 51 sram1: memory@11000000 { 52 compatible = "zephyr,memory-region", "mmio-sram"; 53 reg = <0x11000000 0x2000>; 54 zephyr,memory-region = "SRAM1"; 55 }; 56 57 sysclk: system-clock { 58 compatible = "fixed-clock"; 59 clock-frequency = <48000000>; 60 #clock-cells = <0>; 61 }; 62 63 soc { 64 pinctrl: pinctrl@40081000 { 65 compatible = "ti,cc13xx-cc26xx-pinctrl"; 66 reg = <0x40081000 0x1000>; 67 }; 68 69 gpio0: gpio@40022000 { 70 compatible = "ti,cc13xx-cc26xx-gpio"; 71 reg = <0x40022000 0x400>; 72 interrupts = <0 0>; 73 status = "disabled"; 74 gpio-controller; 75 #gpio-cells = <2>; 76 }; 77 78 trng: random@40028000 { 79 compatible = "ti,cc13xx-cc26xx-trng"; 80 reg = <0x40028000 0x2000>; 81 interrupts = <33 0>; 82 status = "disabled"; 83 }; 84 85 flash_controller: flash-controller@40030000 { 86 compatible = "ti,cc13xx-cc26xx-flash-controller"; 87 reg = <0x40030000 0x4000>; 88 89 #address-cells = <1>; 90 #size-cells = <1>; 91 92 flash0: flash@0 { 93 compatible = "soc-nv-flash"; 94 erase-block-size = <DT_SIZE_K(8)>; 95 write-block-size = <1>; 96 }; 97 }; 98 99 gpt0: timer@40010000 { 100 compatible = "ti,cc13xx-cc26xx-timer"; 101 reg = <0x40010000 0x1000>; 102 interrupts = <15 0 16 0>; 103 interrupt-names = "gpt0a", "gpt0b"; 104 status = "disabled"; 105 106 pwm0: pwm { 107 compatible = "ti,cc13xx-cc26xx-timer-pwm"; 108 #pwm-cells = <1>; 109 status = "disabled"; 110 }; 111 }; 112 113 gpt1: timer@40011000 { 114 compatible = "ti,cc13xx-cc26xx-timer"; 115 reg = <0x40011000 0x1000>; 116 interrupts = <17 0 18 0>; 117 interrupt-names = "gpt1a", "gpt1b"; 118 status = "disabled"; 119 120 pwm1: pwm { 121 compatible = "ti,cc13xx-cc26xx-timer-pwm"; 122 #pwm-cells = <1>; 123 status = "disabled"; 124 }; 125 }; 126 127 gpt2: timer@40012000 { 128 compatible = "ti,cc13xx-cc26xx-timer"; 129 reg = <0x40012000 0x1000>; 130 interrupts = <19 0 20 0>; 131 interrupt-names = "gpt2a", "gpt2b"; 132 status = "disabled"; 133 134 pwm2: pwm { 135 compatible = "ti,cc13xx-cc26xx-timer-pwm"; 136 #pwm-cells = <1>; 137 status = "disabled"; 138 }; 139 }; 140 141 gpt3: timer@40013000 { 142 compatible = "ti,cc13xx-cc26xx-timer"; 143 reg = <0x40013000 0x1000>; 144 interrupts = <21 0 22 0>; 145 interrupt-names = "gpt3a", "gpt3b"; 146 status = "disabled"; 147 148 pwm3: pwm { 149 compatible = "ti,cc13xx-cc26xx-timer-pwm"; 150 #pwm-cells = <1>; 151 status = "disabled"; 152 }; 153 }; 154 155 uart0: uart@40001000 { 156 compatible = "ti,cc13xx-cc26xx-uart"; 157 reg = <0x40001000 0x1000>; 158 interrupts = <5 0>; 159 clocks = <&sysclk>; 160 status = "disabled"; 161 }; 162 163 uart1: uart@4000b000 { 164 compatible = "ti,cc13xx-cc26xx-uart"; 165 reg = <0x4000b000 0x1000>; 166 interrupts = <36 0>; 167 clocks = <&sysclk>; 168 status = "disabled"; 169 }; 170 171 i2c0: i2c@40002000 { 172 compatible = "ti,cc13xx-cc26xx-i2c"; 173 #address-cells = <1>; 174 #size-cells = <0>; 175 reg = <0x40002000 0x1000>; 176 interrupts = <1 0>; 177 clock-frequency = <I2C_BITRATE_STANDARD>; 178 status = "disabled"; 179 }; 180 181 spi0: spi@40000000 { 182 compatible = "ti,cc13xx-cc26xx-spi"; 183 #address-cells = <1>; 184 #size-cells = <0>; 185 reg = <0x40000000 0x1000>; 186 interrupts = <7 0>; 187 status = "disabled"; 188 }; 189 190 spi1: spi@40008000 { 191 compatible = "ti,cc13xx-cc26xx-spi"; 192 #address-cells = <1>; 193 #size-cells = <0>; 194 reg = <0x40008000 0x1000>; 195 interrupts = <8 0>; 196 status = "disabled"; 197 }; 198 199 /* The RTC peripheral backs the kernel system clock and tick timer. */ 200 rtc: rtc@40092000 { 201 compatible = "ti,cc13xx-cc26xx-rtc-timer"; 202 reg = <0x40092000 0x1000>; 203 interrupts = <4 0>; /* interrupt #20 = 4 + 16 */ 204 status = "okay"; /* the system clock timer is mandatory */ 205 }; 206 207 radio: radio@40040000 { 208 compatible = "ti,cc13xx-cc26xx-radio"; 209 status = "disabled"; 210 211 reg = <0x40040000 0x1000 212 0x40041000 0x2000 213 0x40043000 0x1000 214 0x40044000 0x1000>; 215 reg-names = "RFC_PWR", "RFC_DBELL", "RFC_RAT", "RFC_FSCA"; 216 217 ieee802154: ieee802154 { 218 compatible = "ti,cc13xx-cc26xx-ieee802154"; 219 status = "disabled"; 220 }; 221 222 ieee802154g: ieee802154g { 223 compatible = "ti,cc13xx-cc26xx-ieee802154-subghz"; 224 status = "disabled"; 225 }; 226 }; 227 228 wdt0: watchdog@40080000 { 229 compatible = "ti,cc13xx-cc26xx-watchdog"; 230 reg = <0x40080000 0x1000>; 231 interrupts = <14 0>; /* interrupt #30 = 14 + 16 */ 232 status = "disabled"; 233 }; 234 235 adc0: adc@400cb008 { 236 compatible = "ti,cc13xx-cc26xx-adc"; 237 reg = <0x400cb008 0x1>; 238 interrupts = <32 0>; /* interrupt #48 = 32 + 16 */ 239 status = "disabled"; 240 #io-channel-cells = <1>; 241 }; 242 }; 243}; 244 245&nvic { 246 arm,num-irq-priority-bits = <3>; 247}; 248 249&systick { 250 status = "disabled"; 251}; 252