1/*
2 * Copyright (c) 2023 PSICONTROl nv
3 *
4 * SPDX-License-Identifier: Apache-2.0
5 */
6
7#include <st/u5/stm32u5.dtsi>
8
9
10/ {
11	soc {
12		compatible = "st,stm32u595", "st,stm32u5", "simple-bus";
13
14		pinctrl: pin-controller@42020000 {
15			compatible = "st,stm32-pinctrl";
16			#address-cells = <1>;
17			#size-cells = <1>;
18			reg = <0x42020000 0x2800>;
19
20			gpioj: gpio@42022400 {
21				compatible = "st,stm32-gpio";
22				gpio-controller;
23				#gpio-cells = <2>;
24				reg = <0x42022400 0x400>;
25				clocks = <&rcc STM32_CLOCK_BUS_AHB2 0x00000200>;
26			};
27		};
28
29		usart6: serial@40006400 {
30			compatible = "st,stm32-usart", "st,stm32-uart";
31			reg = <0x40006400 0x400>;
32			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x02000000>;
33			resets = <&rctl STM32_RESET(APB1L, 25U)>;
34			interrupts = <126 0>;
35			status = "disabled";
36		};
37
38		i2c5: i2c@40009800 {
39			compatible = "st,stm32-i2c-v2";
40			clock-frequency = <I2C_BITRATE_STANDARD>;
41			#address-cells = <1>;
42			#size-cells = <0>;
43			reg = <0x40009800 0x400>;
44			clocks = <&rcc STM32_CLOCK_BUS_APB1_2 0x00000040>;
45			interrupts = <128 0>, <127 0>;
46			interrupt-names = "event", "error";
47			status = "disabled";
48		};
49
50		i2c6: i2c@40009c00 {
51			compatible = "st,stm32-i2c-v2";
52			clock-frequency = <I2C_BITRATE_STANDARD>;
53			#address-cells = <1>;
54			#size-cells = <0>;
55			reg = <0x40009c00 0x400>;
56			clocks = <&rcc STM32_CLOCK_BUS_APB1_2 0x00000080>;
57			interrupts = <130 0>, <129 0>;
58			interrupt-names = "event", "error";
59			status = "disabled";
60		};
61	};
62};
63