1/*
2 * Copyright (c) 2018 Markus Roppelt
3 *
4 * SPDX-License-Identifier: Apache-2.0
5 */
6
7#include <st/l4/stm32l432.dtsi>
8
9/ {
10	soc {
11		compatible = "st,stm32l433", "st,stm32l4", "simple-bus";
12
13		pinctrl: pin-controller@48000000 {
14			gpiod: gpio@48000c00 {
15				compatible = "st,stm32-gpio";
16				gpio-controller;
17				#gpio-cells = <2>;
18				reg = <0x48000c00 0x400>;
19				clocks = <&rcc STM32_CLOCK_BUS_AHB2 0x00000008>;
20			};
21
22			gpioe: gpio@48001000 {
23				compatible = "st,stm32-gpio";
24				gpio-controller;
25				#gpio-cells = <2>;
26				reg = <0x48001000 0x400>;
27				clocks = <&rcc STM32_CLOCK_BUS_AHB2 0x00000010>;
28			};
29		};
30
31		i2c2: i2c@40005800 {
32			compatible = "st,stm32-i2c-v2";
33			clock-frequency = <I2C_BITRATE_STANDARD>;
34			#address-cells = <1>;
35			#size-cells = <0>;
36			reg = <0x40005800 0x400>;
37			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00400000>;
38			interrupts = <33 0>, <34 0>;
39			interrupt-names = "event", "error";
40			status = "disabled";
41		};
42
43		spi2: spi@40003800 {
44			compatible = "st,stm32-spi-fifo", "st,stm32-spi";
45			#address-cells = <1>;
46			#size-cells = <0>;
47			reg = <0x40003800 0x400>;
48			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00004000>;
49			interrupts = <36 5>;
50			status = "disabled";
51		};
52
53		usart3: serial@40004800 {
54			compatible = "st,stm32-usart", "st,stm32-uart";
55			reg = <0x40004800 0x400>;
56			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00040000>;
57			resets = <&rctl STM32_RESET(APB1L, 18U)>;
58			interrupts = <39 0>;
59			status = "disabled";
60		};
61
62		sdmmc1: sdmmc@40012800 {
63			compatible = "st,stm32-sdmmc";
64			reg = <0x40012800 0x400>;
65			clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00000400>,
66				 <&rcc STM32_SRC_HSI48 CLK48_SEL(0)>;
67			interrupts = <49 0>;
68			status = "disabled";
69		};
70	};
71};
72