1/*
2 * Copyright (c) 2021 Nomono AS
3 *
4 * SPDX-License-Identifier: Apache-2.0
5 */
6
7#include <st/l0/stm32l0.dtsi>
8
9/ {
10	soc {
11		compatible = "st,stm32l051", "st,stm32l0", "simple-bus";
12
13		i2c2: i2c@40005800 {
14			compatible = "st,stm32-i2c-v2";
15			clock-frequency = <I2C_BITRATE_STANDARD>;
16			#address-cells = <1>;
17			#size-cells = <0>;
18			reg = <0x40005800 0x400>;
19			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00400000>;
20			interrupts = <24 0>;
21			interrupt-names = "combined";
22			status = "disabled";
23		};
24
25		spi2: spi@40003800 {
26			compatible = "st,stm32-spi";
27			#address-cells = <1>;
28			#size-cells = <0>;
29			reg = <0x40003800 0x400>;
30			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00004000>;
31			interrupts = <26 3>;
32			status = "disabled";
33		};
34
35		usart1: serial@40013800 {
36			compatible = "st,stm32-usart", "st,stm32-uart";
37			reg = <0x40013800 0x400>;
38			clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00004000>;
39			resets = <&rctl STM32_RESET(APB2, 14U)>;
40			interrupts = <27 0>;
41			status = "disabled";
42		};
43
44		timers22: timers@40011400 {
45			compatible = "st,stm32-timers";
46			reg = <0x40011400 0x400>;
47			clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00000020>;
48			resets = <&rctl STM32_RESET(APB2, 5U)>;
49			interrupts = <22 0>;
50			interrupt-names = "global";
51			st,prescaler = <0>;
52			status = "disabled";
53
54			pwm {
55				compatible = "st,stm32-pwm";
56				status = "disabled";
57				#pwm-cells = <3>;
58			};
59		};
60
61		timers6: timers@40001000 {
62			compatible = "st,stm32-timers";
63			reg = <0x40001000 0x400>;
64			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00000010>;
65			resets = <&rctl STM32_RESET(APB1, 4U)>;
66			interrupts = <17 0>;
67			interrupt-names = "global";
68			st,prescaler = <0>;
69			status = "disabled";
70		};
71
72		eeprom: eeprom@8080000{
73			reg = <0x08080000 DT_SIZE_K(2)>;
74		};
75	};
76};
77