1/*
2 * Copyright (c) 2021 Wouter Cappelle <wouter.cappelle@crodeon.com>
3 *
4 * SPDX-License-Identifier: Apache-2.0
5 */
6
7#include <mem.h>
8#include <st/l0/stm32l010.dtsi>
9
10/ {
11	sram0: memory@20000000 {
12		reg = <0x20000000 DT_SIZE_K(20)>;
13	};
14
15	soc {
16		flash-controller@40022000 {
17			flash0: flash@8000000 {
18				reg = <0x08000000 DT_SIZE_K(128)>;
19			};
20		};
21
22		timers22: timers@40011400 {
23			compatible = "st,stm32-timers";
24			reg = <0x40011400 0x400>;
25			clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00000020>;
26			resets = <&rctl STM32_RESET(APB2, 5U)>;
27			interrupts = <22 0>;
28			interrupt-names = "global";
29			status = "disabled";
30
31			pwm {
32				compatible = "st,stm32-pwm";
33				status = "disabled";
34				#pwm-cells = <3>;
35			};
36		};
37	};
38};
39